6.111 Course Information

Duties Name Email Office Phone
Lectures Chris Terman cjt@mit.edu 32-G790 x3-6038
TAs Ben Gelb bgelb@mit.edu 38-600 x3-7350
Alex Valys avalys@mit.edu
Lab Guru Gim Hom gim@mit.edu 38-644 x4-3373
Prerequisites Students should feel comfortable using computers. A rudimentary knowledge of electrical fundamentals (6.002, 6.071) is assumed. As with all project courses the end-of-term cruch can be an issue, so it would be unwise to take another course that also has a significant design project due at the end of term.
Units 6.111 is a 12 unit (3-7-2) course with a substantial laboratory component (7 hours per week). The final six weeks -- 72 course hours -- of the semester are devoted to the final project.
Lectures TR 2:30p - 4p in 32-141. Lectures are not held during the last six weeks of the course so that you can focus on the final project. See the course calendar for a detailed schedule.
There is no required text for the course, but we recommend the following book if you would like a more thorough treatment of some of the topics covered in lecture.

R. H. Katz, G. Borriello
Contemporary Logic Design, 2nd ed.
Prentice Hall (ISBN 0201308576)
December 2004

There are many good Verilog books; we strongly recommend that you have access to one. Several Verilog books are available for in-lab checkout from the Digital Instrument Room (38-601).

D. E. Thomas, P. R. Moorby
The Verilog Hardware Description Language, 5th ed.
Kluwer Academic Publishers (ISBN 1402070896)
June 2002

S. Palnitkar
Verilog HDL, 2nd ed.
Prentice Hall (ISBN 0130449113)

Handouts On-line versions of the handouts (in PDF) can be found at this website.
Lecture Problems A short problem will be handed out during each lecture and your written solution will be due at the start of the following lecture. These should help you practice the design skills introduced by the lecture. Your solutions will be graded and returned.
Quizzes There are no quizzes or final exam.

The 6.111 lab is located on the sixth floor of Building 38 (room 38-600). During business hours you can enter via the lab doors from the Building 36 elevator lobby. After business hours the sixth floor entrance is locked and alarmed so you need to enter and leave on the fifth floor and take the internal stairs up to the 6.111 lab. The usual hours of operation are

09002345Monday - Thursday
stockroom closes @ 1725
stockroom closes @ 1715
stockroom closed

These times are subject to change, particularly around holidays (detailed holiday lab hour schedule is available here); check the signs near the lab entrance and make your plans accordingly. The lab will be staffed by Teaching Assistants (TAs) or Lab Aides (LAs) for some, but not all, of these hours. Gim staffs the lab Sun-Thu in the late afternoon and evenings until closing time.

Each student will be issued their own lab supplies including a protoboard, a collection of components used in the assignments, a pair of scope probes, a pair of analyzer probes, and some hand tools. While wiring and some debugging can be done at home, most assignments require the use of an oscilloscope, logic analyzer and other special equipment, all of which are available in the lab. The FPGA Laboratory Kit can be found at each lab bench. Additional equipment and parts may be checked out from the Digital Instrument Room (38-601) from 0900 to 1700 Monday through Friday. During other hours some, but not all, of this equipment is available from the fifth floor Instrument Room (38-501).

Remember to put your name on anything that you build in the laboratory and leave unattended, otherwise it may be gone when you return. There are some lockers for the safe storage of your supplies along the 6th floor entry corridor; to get one for the semester apply at the 6th floor instrument room desk.

There are five lab assignments to be completed individually. For each lab you will be asked to turn in a report (or your verilog code) in addition to completing a checkoff with a TA. Checkoffs and reports are due by the end of the day on Thursdays in the 6.111 lab. There is a 20%/day late penalty for work completed 1 to 5 working days after the due date. No credit will be given for unexcused lateness exceeding 5 days.

Note that each lab has multiple, often substantial, tasks you need to complete and it is unlikely that you'll be able to complete the work in one sitting (eg, the day the lab is due). The lab and TAs are very busy just before an assignment is due so please plan accordingly.


6.111 is one of the courses that satisfies the EECS Communication-Intensive (CI-M) third-year class requirement. Even if you have satisfied the requirement in some other way, you will need to prepare a report and its revision as described below.

The writing department will provide feedback on the first version of your Lab #3 report. You are required to submit a revised version, which will then be assigned a final grade by the writing department; this grade will contribute 10% to your final grade in 6.111. The 6.111 staff will also evaluate this report for technical merit and assign a grade; this grade will contribute another 5% to your final grade.


Note: you must complete all the labs before starting the final project. We've learned over the years that if you're struggling with the labs then it's unlikely that you'll be able to successfully complete a final project.

The Final Project is the most important assignment -- you'll get to design an implement a small digital system of your own choosing, working with one or at most two partners. The last six weeks of the term are devoted exclusively to working on the project and its accompanying report. We'll be providing lots of information about the project as the term progresses, but here's a quick list of the project milestones:

  • choosing your partner(s) (10/21)
  • project abstract (10/28)
  • project proposal conference (10/31)
  • project block diagram conference (11/07)
  • project design presentations (11/12, 11/13)
  • project checklist (11/14)
  • project demos and videotaping (12/08, 12/09, 12/10)
  • project report due (12/10)
Collaboration The Departmental Guidelines Relating to Academic Honesty require that we inform you of our expectations regarding permissible academic conduct.

The lecture problems and labs should be done individually. You are welcome to get help from others but the work you hand in must be your own. Copying another person's work or allowing your work to be copied by others is a serious academic offense and will be treated as such by the course staff.

Grading The final grade is determined by your performance on the lecture problems, labs, and final project:
  • Lecture problems: 20%
  • Lab 1: 3%
  • Lab 2: 3%
  • Lab 3: 8%
  • Lab 3 revised written report (CI-M): 10%
  • Lab 4: 8%
  • Lab 5: 8%
  • Final project: 40%
    • Problem definition and architecture: 5%
    • Design (modularity, Verilog): 5%
    • Functionality: 10%
    • Complexity, innovation and risk: 10%
    • Quality and organization of presentation and report: 5%
    • Deadlines and participation: 5%

We construct a histogram of these summary numbers and proceed to discuss the individual performance of each student. Some of the factors considered are:

  • Diligence as measured by the time spent in the lab and attendance at the Project Design Presentations.

  • Completion of all the labs. It is extremely rare for a student to receive an "A" without completing the labs. Of course, it is possible to get a grade lower than "A" even if the labs are complete.

  • Performance on the final project:
    • Students who do not construct a final project or turn in a final report will receive an "F".
    • Project complexity is an important factor in discriminating between an "A" and a "B".

Traditionally, the average performance (and hence grade) has been quite high in 6.111. A large number of students do "A" level work and are indeed rewarded with a grade of "A". The corollary to this is that, since average performance levels are so high, punting any part of the subject can lead to a disappointing grade. It's very important to keep up with the work.

Incompletes will not be given.