R. H. Katz, G. Borriello
Contemporary Logic Design, 2nd ed.
Prentice Hall (ISBN 0201308576)
December 2004

There are many good Verilog books; we strongly recommend that you have access to one. Several Verilog books are available for in-lab checkout from the Digital Instrument Room (38-601).

D. E. Thomas, P. R. Moorby
The Verilog Hardware Description Language, 5th ed.
Kluwer Academic Publishers (ISBN 1402070896)
June 2002

S. Palnitkar
Verilog HDL, 2nd ed.
Prentice Hall (ISBN 0130449113)
2003

The 6.111 lab is located on the sixth floor of Building 38 (room 38-600). During business hours you can enter via the lab doors from the Building 36 elevator lobby. After business hours the sixth floor entrance is locked and alarmed so you need to enter and leave on the fifth floor and take the internal stairs up to the 6.111 lab. The usual hours of operation are

These times are subject to change, particularly around holidays ; check the signs near the lab entrance and make your plans accordingly. The lab will be staffed by Teaching Assistants (TAs) or Lab Aides (LAs) for some, but not all, of these hours. I am generally in the the lab Mon-Thu in the late afternoon and evenings.

Each student will be issued their own lab supplies including a protoboard, a collection of components used in the assignments, a pair of scope probes and some hand tools. While wiring and some debugging can be done at home, most assignments require the use of an oscilloscope, logic analyzer and other special equipment, all of which are available in the lab. The FPGA Laboratory Kit can be found at each lab bench. Additional equipment and parts may be checked out from the course staff.

Remember to put your name on anything that you build in the laboratory and leave unattended, otherwise it may be gone when you return. There are some lockers for the safe storage of your supplies along the 6th floor entry corridor; to get one for the semester please ask the course staff.

There are five lab assignments to be completed individually. For some labs you will be asked to upload your Verilog code in addition to completing a checkoff with a member of the course staff. Checkoffs can happen anytime the lab is staffed and by appointment. There is a 20%/day late penalty for work completed 1 to 5 working days after the due date.

Note that each lab has multiple, often substantial, tasks you need to complete and it is unlikely that you'll be able to complete the work in one sitting (e.g., the day the lab is due). The lab and staff are very busy just before an assignment is due so please plan accordingly.

6.111, starting Fall 2016, is no longer a EECS Communication-Intensive (CI-M) class. For those students under the pre-2016 EECS curriculum 6.111 may used to satisfy the 6.UAP requirement.

While no longer a CI-M, a project proposal, project presentation and a final report will be required. The grade for all these components will contribute 13% to your final grade in 6.111.

Note: you must complete all the labs before starting the final project. We've learned over the years that if you're struggling with the labs then it's unlikely that you'll be able to successfully complete a final project.

The Final Project is the most important assignment -- you'll get to design and implement a small digital system of your own choosing, working with one or at most two partners. The last six weeks of the term are devoted exclusively to working on the project and its accompanying report. We'll be providing lots of information about the project as the term progresses, but here's a quick list of the project milestones. See the project info page for details.

• project teams
• project abstract
• project proposal conference
• project proposal draft
• project block diagram conference
• project design presentations
• project proposal revision (if necessary)
• project checklist meeting
• project demos/checkoff and videotaping
• project report due

The lecture problems and labs should be done individually. You are welcome to get help from others but the work you hand in must be your own. Copying another person's work or allowing your work to be copied by others is a serious academic offense and will be treated as such by the course staff.

• Lecture problems: 16%
• Labs: 34%
  • Lab 1: 2%
  • Lab 2: 4%
  • Lab 3: 9%
  • Lab 4: 11%
  • Lab 5: 8%
• Final project: 35%
  • Deadlines and participation: 8%
  • Problem definition, architecture, design: 10%
  • Functionality: 8%
  • Complexity, innovation and risk: 9%
• Reports, Presentations: 13%
  • Proposal: 2%
  • Presentation: 6%
  • Final Report: 5%
• Participation (lectures, project presentation): 2%

Some of the factors considered in asssign the final grade are:

• Diligence as measured by the time spent in the lab, quality of the lab implementation and attendance at the Project Design Presentations.

• Completion of all the labs. It is extremely rare for a student to receive an "A" without completing all the labs. Of course, it is possible to get a grade lower than "A" even if the labs are complete.

• Performance on the final project:
  • Students who do not construct a final project or turn in a final report will receive an "F".
  • Project complexity is an important factor in discriminating between an "A" and a "B".

Traditionally, the average performance (and hence grade) has been quite high in 6.111. A large number of students do "A" level work and are indeed rewarded with a grade of "A". The corollary to this is that, since average performance levels are so high, punting any part of the subject can lead to a disappointing grade. It's very important to keep up with the work.

Incompletes will not be given.