After final metallization, GaAs IC wafers (like silicon IC wafers) have dielectric insulation and metal interconnection layers totaling approximately 6 microns in thickness covering their entire surface. In the epi-on-electronics process, this coating of dielectric and metal is removed in certain regions to expose the underlying GaAs wafer surface, as illustrated on the left in Figure 1; it is in these openings that the optoelectronic devices will be created. The wafer is then placed in an epitaxy reactor and the desired heterostructures are deposited. Where the GaAs wafer surface has been exposed the deposition is epitaxial; elsewhere, as shown in middle illustration in Figure 1, polycrystalline material forms. The polycrystalline deposit is then removed.
Figure 1 - Cross-sectional views of an epi-on-electronics OEIC in-plane cavity, surface-emitting laser diode (IPSEL) at several points in the process: Left - as reseived from the GaAs IC manufacturer with all electronics processing complete and with windows for epitaxy open; Middle - after MBE growth with epitaxial heterostructure on the exposed substrate and polycrystalline deposit on the dielectric layers; Right - completed IPSEL monolithically integrated with electronics, viewed end-on.
If the thickness of the heterostructure was designed to match that of the original dielectric and metal overcoating, then at this point the wafer surface is essentially again planar. The epitaxial heterostructures are subsequently processed to create the intended optoelectronic devices and to monolithically interconnect them with the pre-existing electronics, which completes the process. The final stucture is illustrated on the right in Figure 1.
The epi-on-electronics technology offers an immediate path to complex, high performance OEICs and has already been demonstrated in a number of application-specific examples. The initial examples involve the integration of light emitting diodes and m-s-m and MESFET photodetectors with neural network decision circuits and digital switches. Professor Clifton Fonstad of MIT is coordinating a multi-investigator team within the National Center for Integrated Photonics Technology (NCIPT) working to expand the menu of optoelectronic devices available for integration (to include surface-emitting laser diodes, photodiodes, modulators and SEEDs, and waveguide devices), to increase the scope of applications for epi-on-electronics OEICs, and to continually refine the overall process. This effort involves interactions between investigators at a number of universities, industrial organizations, and government laboratories.
Recent work by researchers at MIT has shown that gallium arsenide MESFETs fabricated using commercial VLSI processes incorporating refractory metal ohmic contacts and gates, and standard silicon-IC-like multi-level metal interconnect technology, are not adversely effected by several hours at elevated temperatures. This means that these devices will survive the molecular beam epitaxy growth sequence for many III-V optoelectronic device heterostructures. In fact, these MESFETs still function after being annealed at as high as 700¡C, but as Figure 2 illustrates, the room temperature characteristics change for anneals above roughly 470¡C. Thus if established design rules and simulation tools are to be used, the bulk of the epitaxial growth run must be conducted at 470¡C, or less.
Work presently in progress at MIT deals with understanding the physical mechanisms involved in the changes in the MESFET characteristics above 470¡C, with developing device models incorporating any changes that do occur, and with characterizing and simulating circuit performance after high temperature anneals. The objective is to fully understand the high temperature robustness of GaAs MESFET VLSI, and to work with the commercial manufacturers to improve it. This involves work on improving the technology to make it robust to still higher temperatures, and on developing the data and models needed to design circuits which function well even after anneals in excess of 500¡C.
FIGURE 2 in the works!
Figure 2- The average values of enhancement-mode GaAs MESFET transconductance, gm, after three hour anneals in a hydrogen atmosphere at the temperature indicated on the horizontal axes. The triangles are data for devices processed by Vitesse Semiconductor and the circles are for devices processed by Motorola Inc.
It appears now that it is the upper-level interconnect lines that are changing above 470¡C, and that the route to increasing the stability to higher temperatures lies in adjusting the composition of these metals; there appears to be significant room for improvement. It might be argued that the rapidly expanding body of successful research on reduce-temperature III-V epitaxy (see following section) makes this a lower priority item, which is true, but it is also worth noting that any improvement in high temperature stability is certain to improve circuit reliability, whether or not the chips are destined for use in the epi-on-electronics process. It is also undoubtedly true that the higher the temperature the electronics can tolerate, the more options one has for the epitaxy sequences.
Preliminary work simulating ring oscillator test circuits included on Vitesse wafers indicates that models developed thus far predict the general deterioration in performance expected for anneals above 500¡C and the catastrophic failure above 550¡C that Figure 2 presages. In general, however, the simulations done to date under estimate the amount of change seen upon annealing, and the cause for this discrepancy is under investigation.
Most epitaxy of GaAs-based heterostructures is performed at temperatures well above 500¡C; MBE is typically done at 650 to 700¡C, and MOCVD is typically done at even higher temperatures. These temperatures are dictated, for the most part, by the use of AlGaAs wide bandgap layers and the fact that the quality (purity and morphology) of AlGaAs epilayers in general improves as the growth temperature is increased. Several recent developments have changed this situation significantly, however, and there now exists a growing body of work on reduced temperature growth (almost exclusively by MBE) of GaAs-based optoelectronic heterostructures. The first of these developments is an increased understanding of epitaxial growth mechanisms and the use of reduced arsenic overpressures, and of atomic-layer epitaxy (ALE) and migration-enhanced epitaxy (MEE) techniques, to grow high quality heterostructures at as low as 375¡C. The second is the incorporation of narrower bandgap, strained InGaAs layers in GaAs-based heterostructures and the subsequent reduction in the aluminum fraction of wider the bandgap layers in the structures. These design changes have also been used to grow devices at under 500¡C. The third, and perhaps most significant, development is the shift from the AlGaInAs quaternary system to the Al-free InGaAsP quaternary system for many GaAs-based heterostructures. This system has been used to fabricate laser diodes with performance equal to AlGaInAs devices, and is coincidentally best grown at about 500¡C. It is thus an ideal candidate for many epi-on-electronics devices. (Note, however, that heterostructures requiring large conduction band discontinuities and/or large refractive index steps are still best realized in AlGaInAs, if possible.)
Another restriction of conventional molecular beam epitaxy is the initial surface preparation step which typically involves a brief cycle to 600¡C or higher to desorb any oxide layer on the substrate surface. (A thin oxide layer is often intentionally formed during substrate preparation to provide a protective, reproducible film on the substrate surface.) Recently, however, atomic hydrogen has been used to remove this oxide film at temperatures below 400¡C, and a high temperature oxide removal step is no longer essential.
Taken together the rather fortuitous conflux of these recent developments greatly reduce the impact of the 470¡C temperature constraint placed by the GaAs electronics. There is still work that must be done choosing the optimum growth technique and materials combinations for each device type, and designing and demonstrating devices optimized for these new growth techniques and materials, but this is clearly possible.
One of the elegant features of the epi-on-electronics process is that the upper surface of the epitaxial heterostructure can be designed to be coplanar with the top of the dielectric layer stack covering the wafer so that the overall wafer surface is largely planar. This makes post-epitaxy processing extremely straight forward and essentially no different that conventional device processing, once the poly-crystalline deposit has been removed. As a consequence, many of the device structures used, and the associated processing sequences followed, can be imported directly from other programs and sources.
The epi-on-electronics process has been applied to a number of OEIC'S to date fabricated under two main research efforts:
Figure 3 in the works!
Figure 3 - Microphotographs of a 10 by 10 winner-take-all smart pixel array chip for neural network applications being developed in a joint collaboration between the reserach groups of Prof. Demetri Psaltis at Caltech and Prof. Clifton Fonstad at MIT: Left - A section of the array; Right - One element of the array; the LED is grown in the 50 mm-square diamond-shaped area and the upper device is a photo-FET detector.
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