Compiling Verilog and Simulation

ISE and Modelsim will run on any Athena machine. The executables are stored on a server. Vivado executables are stored on the local machines in the 6.111 lab so they run only on lab machines. The best solutions is to use ISE and Vivado locally - either in lab or on your laptop.

There are online Verilog emulators:

• EDA Playground
  This is an all-inclusive environment...it also doesn't require setting up a local environment and lets you run test benches and write your Verilog (which is important). If you use Icarus Verilog version 0.10 as their compiler option (or one of several others).

• Icarus Verilog
  You can download Icarus Verilog on your computer which is easy/hard depending on OS:

• jdoodle is a another one with plug-and-play functionality . It can handle pretty decent sized simulations....you just need to put everything in a single file... An example is the the two example Verilog files from the Verilog simulation tutorial (written for ModelSim which is in ISE on the lab computers):

  Here is an example of jdoodle Verilog.It takes a bit of time but it runs.

  module jdoodle;
      reg reset;
     reg clock;
     reg go;
     wire [1:0] state;
  
     // Instantiate the unit-under-test
     fsm uut (.reset(reset), .clock(clock), .go(go), .state(state));
  
     // Generate the clock
     initial clock <= 0;
     always #5 clock <= !clock; // 5ns half-period = 100MHz
  
     integer i;
     
     initial
       begin
       $display("starting");
  	#100; // Wait for FPGA to come out of reset (GSR clear)
  	go <= 0;
  	reset <= 1; // Assert reset
  	@(negedge clock); // Wait for two falling clock edges
  	@(negedge clock);
  	reset <= 0; // Release reset
  	@(negedge clock);
  	if (state !== 2'h0)
  	  $display("%t: ERROR: FSM not reset!", $time);
  	@(negedge clock);
  	go <= 1;
  	@(negedge clock);
  	go <= 0;
  
  	// Verify that  advances properly
  	for (i=1; i<4; i=i+1)
  	  begin
  	     if (state !== i)
  	       $display("%t: ERROR: FSM in state %d, expected %d!",
  			$time, state, i);
  	     @(negedge clock);
  	  end
  
  	// Verify that  stays zero while  is not asserted
  	for (i=0; i<4; i=i+1)
  	  begin
  	     if (state !== 2'h0)
  	       $display("%t: ERROR: FSM in state %d, expected %d!",
  			$time, state, 0);
  	     @(negedge clock);
  	  end
  	$display("Done Success!!");
  	$stop; // Pasue simulation
  	
       end
  
  
  
  endmodule
  
  module fsm (reset, clock, go, state);
     input reset;
     input clock;
     input go;
     output [1:0] state;
  
     reg [1:0] state;
  
     always @(posedge clock)
       if (reset)
         state <= 0;
       else
         case (state)
  	 2'h0: state <= go ? 2'h1 : 2'h0;
  	 2'h1: state <= 2'h2;
  	 2'h2: state <= 2'h3;
  	 2'h3: state <= 2'h0;
         endcase
  
  endmodule
  

  You can put your Verilog module that you're writing down below and then make your testbench module the jdoodle module and that seems to work:

The above is a fast and quick way to do Lpsets remotely. Don't rely on these toos for final projects.

Joe Steinmeyer 9/2018