wire [31 : 0] BU78_A;
assign BU78_A[0] = n19;
assign BU78_A[1] = n20;
assign BU78_A[2] = n21;
assign BU78_A[3] = n22;
assign BU78_A[4] = n23;
assign BU78_A[5] = n24;
assign BU78_A[6] = n25;
assign BU78_A[7] = n26;
assign BU78_A[8] = n27;
assign BU78_A[9] = n28;
assign BU78_A[10] = n29;
assign BU78_A[11] = n30;
assign BU78_A[12] = n31;
assign BU78_A[13] = n32;
assign BU78_A[14] = n33;
assign BU78_A[15] = n34;
assign BU78_A[16] = n35;
assign BU78_A[17] = n36;
assign BU78_A[18] = n37;
assign BU78_A[19] = n38;
assign BU78_A[20] = n39;
assign BU78_A[21] = n40;
assign BU78_A[22] = n41;
assign BU78_A[23] = n42;
assign BU78_A[24] = n43;
assign BU78_A[25] = n44;
assign BU78_A[26] = n45;
assign BU78_A[27] = n46;
assign BU78_A[28] = n47;
assign BU78_A[29] = n48;
assign BU78_A[30] = n49;
assign BU78_A[31] = n50;
wire [31 : 0] BU78_B;
assign BU78_B[0] = n758;
assign BU78_B[1] = n759;
assign BU78_B[2] = n760;
assign BU78_B[3] = n761;
assign BU78_B[4] = n762;
assign BU78_B[5] = n763;
assign BU78_B[6] = n764;
assign BU78_B[7] = n765;
assign BU78_B[8] = n766;
assign BU78_B[9] = n767;
assign BU78_B[10] = n768;
assign BU78_B[11] = n769;
assign BU78_B[12] = n770;
assign BU78_B[13] = n771;
assign BU78_B[14] = n772;
assign BU78_B[15] = n773;
assign BU78_B[16] = n774;
assign BU78_B[17] = n775;
assign BU78_B[18] = n776;
assign BU78_B[19] = n777;
assign BU78_B[20] = n778;
assign BU78_B[21] = n779;
assign BU78_B[22] = n780;
assign BU78_B[23] = n781;
assign BU78_B[24] = n782;
assign BU78_B[25] = n783;
assign BU78_B[26] = n784;
assign BU78_B[27] = n785;
assign BU78_B[28] = n786;
assign BU78_B[29] = n787;
assign BU78_B[30] = n788;
assign BU78_B[31] = n789;
wire [31 : 0] BU78_Q;
assign n19 = BU78_Q[0];
assign n20 = BU78_Q[1];
assign n21 = BU78_Q[2];
assign n22 = BU78_Q[3];
assign n23 = BU78_Q[4];
assign n24 = BU78_Q[5];
assign n25 = BU78_Q[6];
assign n26 = BU78_Q[7];
assign n27 = BU78_Q[8];
assign n28 = BU78_Q[9];
assign n29 = BU78_Q[10];
assign n30 = BU78_Q[11];
assign n31 = BU78_Q[12];
assign n32 = BU78_Q[13];
assign n33 = BU78_Q[14];
assign n34 = BU78_Q[15];
assign n35 = BU78_Q[16];
assign n36 = BU78_Q[17];
assign n37 = BU78_Q[18];
assign n38 = BU78_Q[19];
assign n39 = BU78_Q[20];
assign n40 = BU78_Q[21];
assign n41 = BU78_Q[22];
assign n42 = BU78_Q[23];
assign n43 = BU78_Q[24];
assign n44 = BU78_Q[25];
assign n45 = BU78_Q[26];
assign n46 = BU78_Q[27];
assign n47 = BU78_Q[28];
assign n48 = BU78_Q[29];
assign n49 = BU78_Q[30];
assign n50 = BU78_Q[31];
wire BU78_CLK;
assign BU78_CLK = n659;
wire BU78_CE;
assign BU78_CE = n660;
C_ADDSUB_V7_0 #(
0 /* c_add_mode*/,
"00000000000000000000000000000000" /* c_ainit_val*/,
1 /* c_a_type*/,
32 /* c_a_width*/,
1 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
1 /* c_b_type*/,
"00000000000000000000000000000000" /* c_b_value*/,
32 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
0 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
31 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
32 /* c_out_width*/,
0 /* c_pipe_stages*/,
"00000000000000000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU78(
.A(BU78_A),
.B(BU78_B),
.Q(BU78_Q),
.CLK(BU78_CLK),
.CE(BU78_CE)
);
wire [11 : 0] BU353_D;
assign BU353_D[0] = n39;
assign BU353_D[1] = n40;
assign BU353_D[2] = n41;
assign BU353_D[3] = n42;
assign BU353_D[4] = n43;
assign BU353_D[5] = n44;
assign BU353_D[6] = n45;
assign BU353_D[7] = n46;
assign BU353_D[8] = n47;
assign BU353_D[9] = n48;
assign BU353_D[10] = n49;
assign BU353_D[11] = n50;
wire [11 : 0] BU353_Q;
assign n1472 = BU353_Q[0];
assign n1473 = BU353_Q[1];
assign n1474 = BU353_Q[2];
assign n1475 = BU353_Q[3];
assign n1476 = BU353_Q[4];
assign n1477 = BU353_Q[5];
assign n1478 = BU353_Q[6];
assign n1479 = BU353_Q[7];
assign n1480 = BU353_Q[8];
assign n1481 = BU353_Q[9];
assign n1482 = BU353_Q[10];
assign n1483 = BU353_Q[11];
wire BU353_CLK;
assign BU353_CLK = n659;
wire BU353_CE;
assign BU353_CE = n660;
C_REG_FD_V7_0 #(
"000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
12 /* c_width*/
)
BU353(
.D(BU353_D),
.Q(BU353_Q),
.CLK(BU353_CLK),
.CE(BU353_CE)
);
wire [9 : 0] BU380_A;
assign BU380_A[0] = n1472;
assign BU380_A[1] = n1473;
assign BU380_A[2] = n1474;
assign BU380_A[3] = n1475;
assign BU380_A[4] = n1476;
assign BU380_A[5] = n1477;
assign BU380_A[6] = n1478;
assign BU380_A[7] = n1479;
assign BU380_A[8] = n1480;
assign BU380_A[9] = n1481;
wire BU380_BYPASS;
assign BU380_BYPASS = n1482;
wire BU380_CLK;
assign BU380_CLK = n659;
wire [10 : 0] BU380_Q;
assign n1506 = BU380_Q[0];
assign n1507 = BU380_Q[1];
assign n1508 = BU380_Q[2];
assign n1509 = BU380_Q[3];
assign n1510 = BU380_Q[4];
assign n1511 = BU380_Q[5];
assign n1512 = BU380_Q[6];
assign n1513 = BU380_Q[7];
assign n1514 = BU380_Q[8];
assign n1515 = BU380_Q[9];
wire BU380_CE;
assign BU380_CE = n660;
C_TWOS_COMP_V7_0 #(
"00000000000" /* c_ainit_val*/,
1 /* c_bypass_enable*/,
1 /* c_bypass_low*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_bypass*/,
1 /* c_has_ce*/,
1 /* c_has_q*/,
0 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
0 /* c_pipe_stages*/,
"00000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
10 /* c_width*/
)
BU380(
.A(BU380_A),
.BYPASS(BU380_BYPASS),
.CLK(BU380_CLK),
.Q(BU380_Q),
.CE(BU380_CE)
);
wire BU459_CLK;
assign BU459_CLK = n659;
wire [0 : 0] BU459_D;
assign BU459_D[0] = n1483;
wire [0 : 0] BU459_Q;
assign n1484 = BU459_Q[0];
wire BU459_CE;
assign BU459_CE = n660;
C_SHIFT_RAM_V7_0 #(
1 /* c_addr_width*/,
"0" /* c_ainit_val*/,
"0" /* c_default_data*/,
2 /* c_default_data_radix*/,
2 /* c_depth*/,
0 /* c_enable_rlocs*/,
0 /* c_generate_mif*/,
0 /* c_has_a*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"null" /* c_mem_init_file*/,
2 /* c_mem_init_radix*/,
0 /* c_read_mif*/,
1 /* c_reg_last_bit*/,
0 /* c_shift_type*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU459(
.CLK(BU459_CLK),
.D(BU459_D),
.Q(BU459_Q),
.CE(BU459_CE)
);
wire BU467_CLK;
assign BU467_CLK = n659;
wire [0 : 0] BU467_D;
assign BU467_D[0] = n1482;
wire [0 : 0] BU467_Q;
assign n1485 = BU467_Q[0];
wire BU467_CE;
assign BU467_CE = n660;
C_SHIFT_RAM_V7_0 #(
1 /* c_addr_width*/,
"0" /* c_ainit_val*/,
"0" /* c_default_data*/,
2 /* c_default_data_radix*/,
2 /* c_depth*/,
0 /* c_enable_rlocs*/,
0 /* c_generate_mif*/,
0 /* c_has_a*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"null" /* c_mem_init_file*/,
2 /* c_mem_init_radix*/,
0 /* c_read_mif*/,
1 /* c_reg_last_bit*/,
0 /* c_shift_type*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU467(
.CLK(BU467_CLK),
.D(BU467_D),
.Q(BU467_Q),
.CE(BU467_CE)
);
defparam BU478.INIT = 'h6a6a;
wire BU478_I0;
assign BU478_I0 = n1484;
wire BU478_I1;
assign BU478_I1 = n1485;
wire BU478_I2;
assign BU478_I2 = n1520;
wire BU478_I3;
assign BU478_I3 = 1'b0;
wire BU478_O;
assign n1926 = BU478_O;
LUT4 BU478(
.I0(BU478_I0),
.I1(BU478_I1),
.I2(BU478_I2),
.I3(BU478_I3),
.O(BU478_O)
);
wire BU479_D;
assign BU479_D = n1926;
wire BU479_C;
assign BU479_C = n659;
wire BU479_CE;
assign BU479_CE = n660;
wire BU479_PRE;
assign BU479_PRE = 1'b0;
wire BU479_Q;
assign n1522 = BU479_Q;
FDPE BU479(
.D(BU479_D),
.C(BU479_C),
.CE(BU479_CE),
.PRE(BU479_PRE),
.Q(BU479_Q)
);
defparam BU483.INIT = 'h0015;
wire BU483_I0;
assign BU483_I0 = n1484;
wire BU483_I1;
assign BU483_I1 = n1485;
wire BU483_I2;
assign BU483_I2 = n1520;
wire BU483_I3;
assign BU483_I3 = n1521;
wire BU483_O;
assign n1945 = BU483_O;
LUT4 BU483(
.I0(BU483_I0),
.I1(BU483_I1),
.I2(BU483_I2),
.I3(BU483_I3),
.O(BU483_O)
);
wire BU484_D;
assign BU484_D = n1945;
wire BU484_C;
assign BU484_C = n659;
wire BU484_CE;
assign BU484_CE = n660;
wire BU484_Q;
assign n1523 = BU484_Q;
FDE BU484(
.D(BU484_D),
.C(BU484_C),
.CE(BU484_CE),
.Q(BU484_Q)
);
defparam BU488.INIT = 'hc0c0;
wire BU488_I0;
assign BU488_I0 = 1'b0;
wire BU488_I1;
assign BU488_I1 = n1485;
wire BU488_I2;
assign BU488_I2 = n1520;
wire BU488_I3;
assign BU488_I3 = 1'b0;
wire BU488_O;
assign n1963 = BU488_O;
LUT4 BU488(
.I0(BU488_I0),
.I1(BU488_I1),
.I2(BU488_I2),
.I3(BU488_I3),
.O(BU488_O)
);
wire BU489_D;
assign BU489_D = n1963;
wire BU489_C;
assign BU489_C = n659;
wire BU489_CE;
assign BU489_CE = n660;
wire BU489_Q;
assign n1519 = BU489_Q;
FDE BU489(
.D(BU489_D),
.C(BU489_C),
.CE(BU489_CE),
.Q(BU489_Q)
);
wire [9 : 0] BU491_A;
assign BU491_A[0] = n1506;
assign BU491_A[1] = n1507;
assign BU491_A[2] = n1508;
assign BU491_A[3] = n1509;
assign BU491_A[4] = n1510;
assign BU491_A[5] = n1511;
assign BU491_A[6] = n1512;
assign BU491_A[7] = n1513;
assign BU491_A[8] = n1514;
assign BU491_A[9] = n1515;
wire BU491_CLK;
assign BU491_CLK = n659;
wire BU491_CE;
assign BU491_CE = n660;
wire BU491_ACLR;
assign BU491_ACLR = 1'b0;
wire BU491_QA_GE_B;
assign n1521 = BU491_QA_GE_B;
C_COMPARE_V7_0 #(
"0" /* c_ainit_val*/,
1 /* c_b_constant*/,
"1111111111" /* c_b_value*/,
1 /* c_data_type*/,
0 /* c_enable_rlocs*/,
1 /* c_has_aclr*/,
0 /* c_has_aset*/,
0 /* c_has_a_eq_b*/,
0 /* c_has_a_ge_b*/,
0 /* c_has_a_gt_b*/,
0 /* c_has_a_le_b*/,
0 /* c_has_a_lt_b*/,
0 /* c_has_a_ne_b*/,
1 /* c_has_ce*/,
0 /* c_has_qa_eq_b*/,
1 /* c_has_qa_ge_b*/,
0 /* c_has_qa_gt_b*/,
0 /* c_has_qa_le_b*/,
0 /* c_has_qa_lt_b*/,
0 /* c_has_qa_ne_b*/,
0 /* c_has_sclr*/,
0 /* c_has_sset*/,
0 /* c_pipe_stages*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
10 /* c_width*/
)
BU491(
.A(BU491_A),
.CLK(BU491_CLK),
.CE(BU491_CE),
.ACLR(BU491_ACLR),
.QA_GE_B(BU491_QA_GE_B)
);
wire [9 : 0] BU527_A;
assign BU527_A[0] = n1506;
assign BU527_A[1] = n1507;
assign BU527_A[2] = n1508;
assign BU527_A[3] = n1509;
assign BU527_A[4] = n1510;
assign BU527_A[5] = n1511;
assign BU527_A[6] = n1512;
assign BU527_A[7] = n1513;
assign BU527_A[8] = n1514;
assign BU527_A[9] = n1515;
wire BU527_CLK;
assign BU527_CLK = n659;
wire BU527_CE;
assign BU527_CE = n660;
wire BU527_ACLR;
assign BU527_ACLR = 1'b0;
wire BU527_QA_EQ_B;
assign n1520 = BU527_QA_EQ_B;
C_COMPARE_V7_0 #(
"0" /* c_ainit_val*/,
1 /* c_b_constant*/,
"0000000000" /* c_b_value*/,
1 /* c_data_type*/,
0 /* c_enable_rlocs*/,
1 /* c_has_aclr*/,
0 /* c_has_aset*/,
0 /* c_has_a_eq_b*/,
0 /* c_has_a_ge_b*/,
0 /* c_has_a_gt_b*/,
0 /* c_has_a_le_b*/,
0 /* c_has_a_lt_b*/,
0 /* c_has_a_ne_b*/,
1 /* c_has_ce*/,
1 /* c_has_qa_eq_b*/,
0 /* c_has_qa_ge_b*/,
0 /* c_has_qa_gt_b*/,
0 /* c_has_qa_le_b*/,
0 /* c_has_qa_lt_b*/,
0 /* c_has_qa_ne_b*/,
0 /* c_has_sclr*/,
0 /* c_has_sset*/,
0 /* c_pipe_stages*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
10 /* c_width*/
)
BU527(
.A(BU527_A),
.CLK(BU527_CLK),
.CE(BU527_CE),
.ACLR(BU527_ACLR),
.QA_EQ_B(BU527_QA_EQ_B)
);
wire [11 : 0] BU543_D;
assign BU543_D[0] = n39;
assign BU543_D[1] = n40;
assign BU543_D[2] = n41;
assign BU543_D[3] = n42;
assign BU543_D[4] = n43;
assign BU543_D[5] = n44;
assign BU543_D[6] = n45;
assign BU543_D[7] = n46;
assign BU543_D[8] = n47;
assign BU543_D[9] = n48;
assign BU543_D[10] = n49;
assign BU543_D[11] = n50;
wire [11 : 0] BU543_Q;
assign n1559 = BU543_Q[0];
assign n1560 = BU543_Q[1];
assign n1561 = BU543_Q[2];
assign n1562 = BU543_Q[3];
assign n1563 = BU543_Q[4];
assign n1564 = BU543_Q[5];
assign n1565 = BU543_Q[6];
assign n1566 = BU543_Q[7];
assign n1567 = BU543_Q[8];
assign n1568 = BU543_Q[9];
assign n1569 = BU543_Q[10];
assign n1570 = BU543_Q[11];
wire BU543_CLK;
assign BU543_CLK = n659;
wire BU543_CE;
assign BU543_CE = n660;
C_REG_FD_V7_0 #(
"000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
12 /* c_width*/
)
BU543(
.D(BU543_D),
.Q(BU543_Q),
.CLK(BU543_CLK),
.CE(BU543_CE)
);
wire [9 : 0] BU570_A;
assign BU570_A[0] = n1559;
assign BU570_A[1] = n1560;
assign BU570_A[2] = n1561;
assign BU570_A[3] = n1562;
assign BU570_A[4] = n1563;
assign BU570_A[5] = n1564;
assign BU570_A[6] = n1565;
assign BU570_A[7] = n1566;
assign BU570_A[8] = n1567;
assign BU570_A[9] = n1568;
wire BU570_BYPASS;
assign BU570_BYPASS = n1569;
wire BU570_CLK;
assign BU570_CLK = n659;
wire [10 : 0] BU570_Q;
assign n1593 = BU570_Q[0];
assign n1594 = BU570_Q[1];
assign n1595 = BU570_Q[2];
assign n1596 = BU570_Q[3];
assign n1597 = BU570_Q[4];
assign n1598 = BU570_Q[5];
assign n1599 = BU570_Q[6];
assign n1600 = BU570_Q[7];
assign n1601 = BU570_Q[8];
assign n1602 = BU570_Q[9];
wire BU570_CE;
assign BU570_CE = n660;
C_TWOS_COMP_V7_0 #(
"00000000000" /* c_ainit_val*/,
1 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_bypass*/,
1 /* c_has_ce*/,
1 /* c_has_q*/,
0 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
0 /* c_pipe_stages*/,
"00000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
10 /* c_width*/
)
BU570(
.A(BU570_A),
.BYPASS(BU570_BYPASS),
.CLK(BU570_CLK),
.Q(BU570_Q),
.CE(BU570_CE)
);
wire BU651_CLK;
assign BU651_CLK = n659;
wire [0 : 0] BU651_D;
assign BU651_D[0] = n1570;
wire [0 : 0] BU651_Q;
assign n1571 = BU651_Q[0];
wire BU651_CE;
assign BU651_CE = n660;
C_SHIFT_RAM_V7_0 #(
1 /* c_addr_width*/,
"0" /* c_ainit_val*/,
"0" /* c_default_data*/,
2 /* c_default_data_radix*/,
2 /* c_depth*/,
0 /* c_enable_rlocs*/,
0 /* c_generate_mif*/,
0 /* c_has_a*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"null" /* c_mem_init_file*/,
2 /* c_mem_init_radix*/,
0 /* c_read_mif*/,
1 /* c_reg_last_bit*/,
0 /* c_shift_type*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU651(
.CLK(BU651_CLK),
.D(BU651_D),
.Q(BU651_Q),
.CE(BU651_CE)
);
wire BU659_CLK;
assign BU659_CLK = n659;
wire [0 : 0] BU659_D;
assign BU659_D[0] = n1569;
wire [0 : 0] BU659_Q;
assign n1572 = BU659_Q[0];
wire BU659_CE;
assign BU659_CE = n660;
C_SHIFT_RAM_V7_0 #(
1 /* c_addr_width*/,
"0" /* c_ainit_val*/,
"0" /* c_default_data*/,
2 /* c_default_data_radix*/,
2 /* c_depth*/,
0 /* c_enable_rlocs*/,
0 /* c_generate_mif*/,
0 /* c_has_a*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"null" /* c_mem_init_file*/,
2 /* c_mem_init_radix*/,
0 /* c_read_mif*/,
1 /* c_reg_last_bit*/,
0 /* c_shift_type*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU659(
.CLK(BU659_CLK),
.D(BU659_D),
.Q(BU659_Q),
.CE(BU659_CE)
);
defparam BU670.INIT = 'ha9a9;
wire BU670_I0;
assign BU670_I0 = n1571;
wire BU670_I1;
assign BU670_I1 = n1572;
wire BU670_I2;
assign BU670_I2 = n1607;
wire BU670_I3;
assign BU670_I3 = 1'b0;
wire BU670_O;
assign n2213 = BU670_O;
LUT4 BU670(
.I0(BU670_I0),
.I1(BU670_I1),
.I2(BU670_I2),
.I3(BU670_I3),
.O(BU670_O)
);
wire BU671_D;
assign BU671_D = n2213;
wire BU671_C;
assign BU671_C = n659;
wire BU671_CE;
assign BU671_CE = n660;
wire BU671_PRE;
assign BU671_PRE = 1'b0;
wire BU671_Q;
assign n1609 = BU671_Q;
FDPE BU671(
.D(BU671_D),
.C(BU671_C),
.CE(BU671_CE),
.PRE(BU671_PRE),
.Q(BU671_Q)
);
defparam BU675.INIT = 'h0046;
wire BU675_I0;
assign BU675_I0 = n1571;
wire BU675_I1;
assign BU675_I1 = n1572;
wire BU675_I2;
assign BU675_I2 = n1607;
wire BU675_I3;
assign BU675_I3 = n1608;
wire BU675_O;
assign n2232 = BU675_O;
LUT4 BU675(
.I0(BU675_I0),
.I1(BU675_I1),
.I2(BU675_I2),
.I3(BU675_I3),
.O(BU675_O)
);
wire BU676_D;
assign BU676_D = n2232;
wire BU676_C;
assign BU676_C = n659;
wire BU676_CE;
assign BU676_CE = n660;
wire BU676_Q;
assign n1610 = BU676_Q;
FDE BU676(
.D(BU676_D),
.C(BU676_C),
.CE(BU676_CE),
.Q(BU676_Q)
);
defparam BU680.INIT = 'h3030;
wire BU680_I0;
assign BU680_I0 = 1'b0;
wire BU680_I1;
assign BU680_I1 = n1572;
wire BU680_I2;
assign BU680_I2 = n1607;
wire BU680_I3;
assign BU680_I3 = 1'b0;
wire BU680_O;
assign n2250 = BU680_O;
LUT4 BU680(
.I0(BU680_I0),
.I1(BU680_I1),
.I2(BU680_I2),
.I3(BU680_I3),
.O(BU680_O)
);
wire BU681_D;
assign BU681_D = n2250;
wire BU681_C;
assign BU681_C = n659;
wire BU681_CE;
assign BU681_CE = n660;
wire BU681_Q;
assign n1606 = BU681_Q;
FDE BU681(
.D(BU681_D),
.C(BU681_C),
.CE(BU681_CE),
.Q(BU681_Q)
);
wire [9 : 0] BU683_A;
assign BU683_A[0] = n1593;
assign BU683_A[1] = n1594;
assign BU683_A[2] = n1595;
assign BU683_A[3] = n1596;
assign BU683_A[4] = n1597;
assign BU683_A[5] = n1598;
assign BU683_A[6] = n1599;
assign BU683_A[7] = n1600;
assign BU683_A[8] = n1601;
assign BU683_A[9] = n1602;
wire BU683_CLK;
assign BU683_CLK = n659;
wire BU683_CE;
assign BU683_CE = n660;
wire BU683_ACLR;
assign BU683_ACLR = 1'b0;
wire BU683_QA_GE_B;
assign n1608 = BU683_QA_GE_B;
C_COMPARE_V7_0 #(
"0" /* c_ainit_val*/,
1 /* c_b_constant*/,
"1111111111" /* c_b_value*/,
1 /* c_data_type*/,
0 /* c_enable_rlocs*/,
1 /* c_has_aclr*/,
0 /* c_has_aset*/,
0 /* c_has_a_eq_b*/,
0 /* c_has_a_ge_b*/,
0 /* c_has_a_gt_b*/,
0 /* c_has_a_le_b*/,
0 /* c_has_a_lt_b*/,
0 /* c_has_a_ne_b*/,
1 /* c_has_ce*/,
0 /* c_has_qa_eq_b*/,
1 /* c_has_qa_ge_b*/,
0 /* c_has_qa_gt_b*/,
0 /* c_has_qa_le_b*/,
0 /* c_has_qa_lt_b*/,
0 /* c_has_qa_ne_b*/,
0 /* c_has_sclr*/,
0 /* c_has_sset*/,
0 /* c_pipe_stages*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
10 /* c_width*/
)
BU683(
.A(BU683_A),
.CLK(BU683_CLK),
.CE(BU683_CE),
.ACLR(BU683_ACLR),
.QA_GE_B(BU683_QA_GE_B)
);
wire [9 : 0] BU719_A;
assign BU719_A[0] = n1593;
assign BU719_A[1] = n1594;
assign BU719_A[2] = n1595;
assign BU719_A[3] = n1596;
assign BU719_A[4] = n1597;
assign BU719_A[5] = n1598;
assign BU719_A[6] = n1599;
assign BU719_A[7] = n1600;
assign BU719_A[8] = n1601;
assign BU719_A[9] = n1602;
wire BU719_CLK;
assign BU719_CLK = n659;
wire BU719_CE;
assign BU719_CE = n660;
wire BU719_ACLR;
assign BU719_ACLR = 1'b0;
wire BU719_QA_EQ_B;
assign n1607 = BU719_QA_EQ_B;
C_COMPARE_V7_0 #(
"0" /* c_ainit_val*/,
1 /* c_b_constant*/,
"0000000000" /* c_b_value*/,
1 /* c_data_type*/,
0 /* c_enable_rlocs*/,
1 /* c_has_aclr*/,
0 /* c_has_aset*/,
0 /* c_has_a_eq_b*/,
0 /* c_has_a_ge_b*/,
0 /* c_has_a_gt_b*/,
0 /* c_has_a_le_b*/,
0 /* c_has_a_lt_b*/,
0 /* c_has_a_ne_b*/,
1 /* c_has_ce*/,
1 /* c_has_qa_eq_b*/,
0 /* c_has_qa_ge_b*/,
0 /* c_has_qa_gt_b*/,
0 /* c_has_qa_le_b*/,
0 /* c_has_qa_lt_b*/,
0 /* c_has_qa_ne_b*/,
0 /* c_has_sclr*/,
0 /* c_has_sset*/,
0 /* c_pipe_stages*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
10 /* c_width*/
)
BU719(
.A(BU719_A),
.CLK(BU719_CLK),
.CE(BU719_CE),
.ACLR(BU719_ACLR),
.QA_EQ_B(BU719_QA_EQ_B)
);
wire [9 : 0] BU273_addra;
assign BU273_addra[9] = n1515;
assign BU273_addra[8] = n1514;
assign BU273_addra[7] = n1513;
assign BU273_addra[6] = n1512;
assign BU273_addra[5] = n1511;
assign BU273_addra[4] = n1510;
assign BU273_addra[3] = n1509;
assign BU273_addra[2] = n1508;
assign BU273_addra[1] = n1507;
assign BU273_addra[0] = n1506;
wire [9 : 0] BU273_addrb;
assign BU273_addrb[9] = n1602;
assign BU273_addrb[8] = n1601;
assign BU273_addrb[7] = n1600;
assign BU273_addrb[6] = n1599;
assign BU273_addrb[5] = n1598;
assign BU273_addrb[4] = n1597;
assign BU273_addrb[3] = n1596;
assign BU273_addrb[2] = n1595;
assign BU273_addrb[1] = n1594;
assign BU273_addrb[0] = n1593;
wire BU273_clka;
assign BU273_clka = n659;
wire BU273_clkb;
assign BU273_clkb = n659;
wire [16 : 0] BU273_dina;
assign BU273_dina[16] = 1'b0;
assign BU273_dina[15] = 1'b0;
assign BU273_dina[14] = 1'b0;
assign BU273_dina[13] = 1'b0;
assign BU273_dina[12] = 1'b0;
assign BU273_dina[11] = 1'b0;