6.111 Handouts

  • L01: Digital Abstraction, 9/7/05 [PDF]
  • L02: Logic Gates, 9/9/05 [PDF]
  • L03: Logic Synthesis, 9/12/05 [PDF]
  • L04: Introduction to Verilog, 9/14/05 [PDF]
  • L05: Sequential Logic, 9/16/05 [PDF]
  • L06: FSMs, 9/21/05 [PDF]
  • L07: FSM/FPGA demo, 9/26/05 [PDF | zipfile of verilog | 16-digit hex display]
  • L08: Memories, 9/28/05 [PDF]
    • CI-M slides: 6.111 Papers [PDF]
  • L09: Memories and System Integration , 9/30/05 [PDF]
  • L10: Reconfigurable Logic, 10/3/05 [PDF]
  • L11: Lab 3 & Final Project, 10/5/05 [PDF]
  • L12: Arithmetic: Addition & Subtraction, 10/12/05 [PDF]
  • L13: Arithmetic: Multiplication, 10/14/05 [PDF]
  • L14: Analog Building Blocks, 10/17/05 [PDF]
  • L15: Video Circuits, 10/19/05 [PDF]
  • L16: Power, Fault tolerance, and quantum computation, 10/24/05 [PDF]
  • L17: Verilog Events, FSMs++, FPGAs @ home, 10/26/05 [PDF]

Lab 1
    checkoff and report due 5pm on 9/23

  • Lab 1 Handout [PDF]
  • Lab 1 Report Template [PDF]

  • lab1.v

  • 74LS00 data sheet [PDF]
  • 74LS04 data sheet [PDF]
  • 74LS163 data sheet [PDF]
  • 74LS393 data sheet [PDF]
  • HCMOS Family Specifications [PDF]
  • 7-segment LED pinout [PDF]

Lab 2

Lab 3

Lab 4

Sample Code for Labkit
Module Description HDL Module File(s) Sample Bit file
16-Digit HEX display display_16hex.v (updated 14-Nov-05 to be completely synchronous) sample bitfile
Sound effects generator (sample) sfx.v sample bitfile
Video display of character strings cstringdisp.v, font_rom.v, font_rom.ngo (for ISE63) font_rom.zip (all font_rom.*) sample (includes has XGA colorbar test) sample tested under ISE6.3 bitfile
Video display of hex digits (a parameterizable number); this example also shows how to share one font rom among multiple pixel generating modules big_vga_hexdisp4.v sample(zipfile includes font rom) bitfile
Display ascii string on dot LEDs display_string.v sample bitfile
PS/2 keyboard input ps2_kbd.v ps2_kbd_sample (video display) ps2_kbd_sample2 (dot LED display) bitfile | bitfile
RC servo motor control rc_motor.v rc_motor_sample bitfile
Beta2 system-on-a-chip for 6.111 labkit labkit_beta2demo.zip html bitfile
NTSC video decoder/digitizer (b&w) example video_decoder.v video_decoder_sample.zip bitfile
ADC example (uses peripheral module from Digilent adc_driver.v adc_driver_sample.v bitfile
ps/2 mouse input ps2_mouse.v ps2_mouse_sample.v vga_sync.v bitfile
VGA display of image from ROM vga_romdisp.v vga_romdisp_sample.zip pgm2coe.py bitfile
Example FFT usage: performs simple 256-point 8-bit FFT and displays power spectrum in VGA window fft_sample.v fft_sample.zip twos2off.v vga_graph2_buf.v
Direct Digital Synthesis (DDS) generation of audio tones dds_sample.v dds_sample.zip dds_sample-ise63.zip ac97_audio.v
ZBT RAM example - displays b&w NTSC video in 1024x768 window zbt_6111.v zbt_6111_sample.zip zbt_6111_sample.v ntsc2zbt.v
Module jtag2mem for bi-directional communication between PC and FPGA using JTAG port and BSCAN_VIRTEX2 (via parallel port programmer). The demo allows PC download to & upload from video memory displaying characters on VGA grid of text characters. jtag2mem.v
jtag2mem_6111.zip jtag2mem_6111.v vga_textgrid22x.v
Example demonstrating a 15-sample FIR filter with 8-bit coefficients, processing 48 kHz audio, with a 20-bit DDS test signal. The coefficients can be loaded in from the PC using jtag2mem. filter_sample.v

  • Midterm with solutions [PDF]


  • Texas Instruments Digital Logic Pocket Data Book [PDF]
    • Pin Assignment Diagrams [PDF]