- In order to create sound, data needs
to be sent to the AC97. Typically, the data is stored on a ROM.
This MATLAB script converts wav file on a PC to COE file.
Instructions are in the MATLAB script. The COE file is the actual
data to be sent to the AC97 and is used to create the
ROM. For long songs, you will need to down sample from 48Khz
to 6khz in order to play a long song ala the audio lab.
The lecture notes on Memory shows how to create a rom.
Credit to Yuta Kuboyama of
the 6.111 Conductor Hero Project Team for the MATLAB script.
Many audio files you'll want to use with your project have a sample rate other than the
ac97's default rate of 48kHz. If you convert such a file to coe and play it on the board
at 48kHz without upsampling or downsampling, it will play back too fast or too slow and sound terrible. This MATLAB script can be used to check the sample rate of
a wav file, and to convert to any desired sample rate.
Note: for best results, use MATLAB R2012b (8.0) or newer. To use 8.0 on Athena, run
add matlab; matlab -ver 8.0
Another approach and easier, is to play the audio through the AC97 and store the samples in flash memory.
- This document describes the NTSC camera interface.
This sample Verilog decodes and display a BW
image. In order to display color, the sample Verilog will need to be modified for
color. For detecting color, it may be more effective to base color selection in HSV space.
RGB2HSV does the RGB to HSV converison. In order to use
RGB2HSV, an appropriate divider module will must be created with the IP Core generator.
The video camera input is the bottom connector.
- It turns out that ZBT memory timing is extremely tricky and extra care must be
followed when using ZBT memory. The ZBT code in the earlier NSTC sample
verilog (not recommended) took a quick and dirty way out by inverting clock to the ZBT
(from zbt_6111.v)
assign ram_clk = ~clk;
The period of a 65Mhz clock is 15ns. When propagation delay stack up in wrong direction (with a 15ns inverted clock, you have only 7.5ns of propagation delay budget), inverting the clock will no longer suffice. Fortunately, Nathan Ickes, the labkit designer took this into account and provided for deskewed clocks. However, using it can be tricky since the deskewed clock utilizes I/O flip-flops (OFDDRRSE) for the RAM and feedback clock outputs. These special primitives are actually part of the I/O driver circuitry on the FPGA. This means that you will not be able to use these inputs or outputs anywhere else in your code. The net result is that the clocks must go directly to the ram and not to any other instantiated module. His sample ramclock module must be part of the top level labkit module.
An example of correctly using ramclock is shown the updated sample NTSC Verilog .
Since the hold time for the ZBT is only 0.5ns, using deskewed clocks should make for a clean design. This document describes the details of the deskewing:
"Inside the FPGA, clocks are distributed using dedicated clock trees, which ensure that the clock signals reach every flip-flop relatively simultaneously. If the clock inputs of the ZBT memories are driven by outputs of the FPGA, then the clock signal at the memories will be delayed by the sum of the propagation delay through the FPGA output pins and the propagation delay of the PCB trace.
To correct this skew at the memory devices, we need to drive the ZBT clock inputs with a phase-shifted version of the clock, so that the rising clock edge reaches the memory devices at the same time that it reaches all the registers in the FPGA. To generate this phase-shifted clock, a delay-locked loop (DLL) is used. DLLs are fundamentally analog components. There is no way to infer a DLL using Verilog code, so they must be instantiated. The Xilinx library component containing a DLL is the digital clock manager, or DCM."
- In order to play images, JPG files must be converted to RGB values
as described here.
We have created a MATLAB script that does conversion.
Instructions are included in the MATLAB script.
Here is a sample Verilog for displaying an
image and instructions for creating the ROM. This bitfile
displays an image with 256 colors. SWITCH[0]
toggles between black/white and color. UP/DOWN/LEFT/RIGHT moves the cross hair. For those projects
using RGB color selection, you can use the cross hair to display RGB values on the hex display.
Better yet, convert to HSV and see if H (hue) is a better criteria for color selection.
The left most 6 digits displays the 8 bit RGB values, respectively, in hex format. The
right most 6 digits displays
the XY coordinates respectively in hex format.
Credit to Edgar Twigg of the 6.111 Conductor Hero Project Team for the MATLAB script.
In many cases, the left most column of pixels in the image is wrong. That's because of the pipeline delays in getting the pixels to the video DAC. The clean rigorous approach is to delay hsync, vsync, blank and a control bit by the correct clock cycles. Then use the control bit to select the pixels to be sent to the video display. In this way, the pixel values will be in sync with the video control signals.
- Math functions and other digital processing designs can be generated and synthesised using the
IP Core generator.
An example of generating a divider is shown in the Multiplier lecture.
Note that synthesis time goes up significantly
as the bit width is increased - so resist the temptation to use the maximums.
Note that 18 bit multipliers are built in. Use IP Core if you need more bits of
resolution.
- FFT cannot be generated with ISE 10. The work around is to create
the FFT on the one workstation running ISE 8, save
the project and move the project to ISE 10. When
the FFT is first compiled, highlight the FPGA Chip, and select NGC/NGO
as the top level source. Ater compilation revert back to HDL.
- Text can be displayed on the 16 5x8 dot display. This
sample file
creates text. The dots are driven by
display_string.v.
- We have Verilog modules from Fall 2005
that may be useful for your projects. The sample files
are toward the end of the webpage. Unlike the lab Verilog modules in the course, these files have not been vigorously tested.
- Given that you will be working in teams, we highly recommend using a version control system. There are many reasons for doing so, but the primary reason is that you each person in the team has full control repository. If you commit your code intelligently, you don't have to worry about the situation where you make some series of changes and can't figure out what you changed to cause things to stop working and can't go back to your earlier code! Check it out
git.html.
Credit to Joseph Colosimo, MIT '12
- Can be read or written byte a time Can only be erased block
at a time Erasure sets bits to 1. Location can be
re-written if the new bit is zero.
The Labkit has 128Mbits of memory in 1Mbit blocks consisting
of a 3 Volt Intel StrataFlash® Memory (28F128J3A). The
device has a 100,000 min erase cycle per block.
Flash memory has some limitations. It can be read one byte
at a time. However, it can be erased only block at a time.
Erasures sets the bits to a 1. After erasure, the bytes can
be written. Locations can actually be written without
erasure if the bit pattern goes from 1 to zero.
Block erasures takes one second. It takes 15 minutes to
write entire flash ROM.
More information including Verilog for the labkit is included in
flash_IO.zip. The sample Verilog sets
a limit on the max address for the flash. You should change according to your needs.
Credit to Edgar Twigg of the 6.111 Conductor Hero Project Team
- Massive amounts of data such as
music, images, etc, can be transfer from a PC to the labit
via a
FTDI UM245R USB-to-FIFO or
FTDI UM245M USB-to-FIFO
module for bidirectional data
transfer using a handshake protocol with selectable baud rates.
More information including Verilog for the labkit is included in
USB_transfer.zip. The sample Verilog is for
the UM245M.
Credit to Edgar Twigg of the 6.111 Conductor Hero Project Team.
- This document gives an overview
of serial data.
- This document gives an overview on using the SD card and audio
with the Nexys4. Verilog:
labkit_sd.v,
sd_controller.v,
audio_PWM.v