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6.111 Labkit  

 FPGA Labkit

for 6.111 Introduction to Digital Systems

6.111 homeLabkit homeTest Programs → Audio and Video Tests

Audio and Video Tests

by Nathan Ickes

Introduction

This test verifies that the labkit's audio and video components are working properly. This includes audio input and output, VGA output, and TV (composite and s-video) input and output.

Setup

Most components of this test program require external equipment in order to generate inputs for the labkit, or reproduce signals output by the labkit.

Testing the audio codec requires

  • A stereo audio source (e.g., an MP3 player) and appropriate cables to connect it to the labkit's RCA audio input jacks
  • Headphones or amplified speakers with a 1/8″ stereo connector for the labkit's headphone out jack
  • Cables to connect the above headphones or speakers to the labkit's line-level RCA audio output jacks
  • A PC microphone, with an internal preamp and a 1/8″ stereo connector for the labkit's microphone jack.

Testing the VGA output port requires a computer monitor capable of displaying 1024×768 @ 75Hz, and a cable to connect it to the labkit's 15-pin VGA connector.

Testing the labkit's TV components requires

  • An NTSC monitor, with composite and s-video inputs, and cables to connect it to the labkit's RCA composite input jack, and mini-DIN s-video jack.
  • An NTSC composite video source (such as a camera, VCR, or DVD player) and the appropriate cable for the labkit's RCA input jack.
  • An NTSC s-video source (such as a VCR or DVD player), and the appropriate cable to connect it to the labkit.

Precompiled bitstreams for this test can be downloaded below

Audio Test Procedure

When the FPGA has been configured using the above bitstreams and all of the slide switches are in their down position, the alphanumeric display should read

As indicated by the display ("V:0"), the audio output volume is initially set at its lowest setting. The volume can be adjusted over the range of 0-15 using the up and down pushbuttons.

After loading the avtest bitstream into the FPGA, plug a pair of headphones or amplified speakers into the labkit's headphone out jack. To test the audio codec's "beep" input, press the enter pushbutton: a shrill tone should be heard in the headphones. This tone is actually a digital square wave generated by the FPGA, which is mixed into the final stage of the codec's output amplifier. Thus, this beep test should work, even if the rest of the does not.

Next, connect a line-level audio source to the left and right audio inputs, and plug a PC amplified microphone into the microphone jack. The three rightmost slide switches (2-0) control what is heard in the headphones, according to the table below. For all of the above settings, no static or other noise should be heard in the audio output, even at the highest volume settings.

Switch 2 Switch 1 Switch 0 Display Output
Down Down Down LIN From line-level inputs
X Down Up SIL Silence
X Up Down SIN Sine wave
X Up Up SQR Square wave
Up Down Down MIC From microphone

For the silence, sine wave, and square wave settings, data for the audio output DACs is directly generated by the FPGA. For the line-in and microphone settings, the corresponding input is sampled by the audio codec's ADC, the samples are sent to the FPGA over the AC'97 link, and the FPGA immediately retransmits the samples back to the codec's DAC for regeneration on the audio outputs. These loopback tests therefore test the entire audio codec, as well as the AC'97 between the codec and the FPGA.

The line-level audio outputs are driven with the same waveforms as the headphone outputs.

VGA Test Procedure

When a monitor is connected to the labkit's VGA output connector, the following pattern should be displayed on the monitor

TV Test Procedure

Connect a composite video source to the labkit's composite video input jack, and s-video source to the s-video input jack, and a composite-input monitor to the labkit's composite video output jack. Slide switches 3 and 4 control whether the labkit's output displays colorbars (generated by the ADV7194 video encoder itself), the MIT logo (generated by a state machine in the FPGA), or a replica of the video signal on either the s-video or composite input jacks.

Switch 4 Switch 3 Display Output
Down Down CLRBARS Colorbars
Down Up MITLOGO MIT Logo
Up Down COMPOSI From composite input
Up Up S-VIDEO From s-video input

Signals Available for Probing

Verilog Signal Name Description Logic Analyzer User I/O
clock_27mhz Labkit clock (27MHz) Pad 1, clock Bank 1, pin 12
tv_out_ycrcb YCrCb data to ADV7194 (10 bits) Pod 1, channels 9-0 Bank 1, pins 9-0
tv_out_i2c_clock I2C clock for ADV7194 Pod 1, channel 15 Bank 1, pin 11
tv_out_i2c_data I2C data for ADV7194 Pod 1, channel 14 Bank 1, pin 10
tv_in_line_clock1 Video decoder line clock (27MHz) Pad 1, clock Bank 1, pin 12
tv_in_ycrcb YCrCb data from ADV7185 (10 bits) Pod 2, channels 9-0 Bank 1, pins 22-13
tv_in_i2c_clock I2C clock for ADV7185 Pod 2, channel 15 Bank 1, pin 24
tv_in_i2c_data I2C data for ADV7185 Pod 2, channel 14 Bank 1, pin 23

Source Code

MIT 6.111 Introduction to Digital Systems, Updated April 11, 2005