MIDI Controlled Sample-Based Synthesizer

Amir Hirsch and Andrew Leiserson

Design and Debugging

Design

Andy

My basic design strategy focused on developing simple modules that would allow a functional test early on but were extensible enough that they could be extended to more complicated functionality as the project progressed without redoing work that was already done. In general this strategy was successful. My early work involved the MIDI, PS/2, AC97, and display interfaces. The interface modules were done in a clean enough fashion that they could all be connected to later versions of the rest of the system with no changes at all.

Amir

I spent the first stage of the design process writing C code to run the interpolation and the filter on my computer in order to determine what kind of functionality I needed in my DPU. After I was satisfied with the results of the C code, I proceeding to create the datapath which I tested extensively in simulation. After realizing the difficultly of trying to convert assembly code to bytecode by hand, I knew I needed a better approach and thus wrote an assembler in Scheme. I was able to put the output of the assembler into the ROM file which made it easy to test each of the DPU functions. The SGU controller was a relatively straightforward FSM. In one sample period the interpolation is computed and in the second sample period the filter. This "pipelined" design created a 3 sample-period latency, but allowed the entire operation of the SGU to occur under in under 100 clock cycles.

Debugging

During the development of the AC97 controller, a problem was encountered with the Xilinx XST synthesis tool. When a bit of a register was assigned to with a mathematical expression such as " register[256 - bit_count] = data_in; ", the optimizer concluded that the register signal was constant and optimized it out of the design. A workaround was developed, using a separate signal for the index as follows:

assign index = 256 - bit_count;
register[index] = data_in;

Although this workaround solved the synthesis problem, it is still not an efficient implementation logic-wise. The final implementation of the AC97 Controller used shift registers to minimize the amound of logic.

The bidirectional DPU bus also caused some problems with the "Place and Route" function of the Xilinx tool. Specifically, the tool decided that the longest signal path was an infinite loop through the DPUs. This made the tool determine that our clock speed must be set too low for the computation to process in time. In order to fix this problem, we separated the bidirection bus into several one-way buses: one going from the SGU to all of the DPU's and one for each DPU to send output to the SGU.