Hybrid integration involves combining optoelectronic devices and integrated circuits in the same package or substrate. This can be done using traditional hybrid techniques for simply combining packaged devices on a ceramic substrate, but the device density of the resulting optoelectronic integrated circuit (OEIC) is very low and many of the advantages of using optics are lost. Consequently, alternative hybrid techniques have been proposed to increase device density while maintaining manufacturability. Currently the most successful such techniques involve flip-chip/solder-ball or -bump integration of discrete optoelectronic devices on multi-chip modules or directly on silicon IC chips, but even these techniques consume an inordinate amount of area and even higher densities are needed. A possible solution is the use of specially thinned discrete devices (and, ultimately, moderate sized arrays of devices) which can be flip-bonded to IC chips with much smaller bond pads, and thus with more efficient use of space (and even some stacking of devices). Prof. N. Jokerst and her students at Georgia Tech have done the most work developing this technology, which they term " epitaxial lift-off". This technique was first demonstrated by E. Yablonovich at BellCore (now at UCLA).
Hybrid integration offers an immediate solution to certain OEIC needs, and it may always be the technology of choice when many different kinds of devices need to be combined, but monolithic integration will always be superior in terms of speed, device density, system reliability, ultimate complexity, and manufacturablity. A major difficulty with monolithic integration is that the most widely used, highly developed material for integrated electronics, silicon, is not useful for many optoelectronic devices and thus one must either monolithically integrate III-V optoelectronic devices on silicon, or one must utilize III-V electronics.
Monolithic integration of InGaAlAs and InGaAsP heterostructures on silicon (a process generically called GaAs-on-Si) is attractive because it would allow one to make use of the wealth of silicon BiCMOS electronics integrated circuit technology existing today. Unfortunately, III-V epitaxy on silicon (or vice versa) is made difficult by the facts that the lattice constants of GaAs and Si differ by 4%, and that the thermal expansion coefficients differ by almost 50%. The lattice mismatch can be overcome by special growth initiation techniques and interfacial buffer layers, but the thermal mismatch is more troublesome. Significant numbers of defects (and even cracks) are introduced as GaAs-on-Si structures are cooled from the growth temperature to room temperature, and the III-V layers are under severe tension, which reduces device lifetimes dramatically, reduces reliability, and in general adversely effects performance. The most promising solution to this incompatibility involves introducing an AlAs layer between the growth-initiation layers and the active device heterostructures, and subsequently etching this AlAs layer away to physically separate the III-V device structure from the Si, but otherwise leave it monolithically integrated on the chip. Preliminary studies at MIT have shown that the separated structure can be thermally annealed to remove the thermally induced strain and defects (significantly improving the material quality and device performance), but much more work remains to be done.
The difficulty of monolithic integration on silicon, and steady advances in the levels of electronic integration demonstrated on III-V substrates have led to a shift of emphasis to monolithic integration on either gallium arsenide or indium phosphide. Two approaches are being pursued. The first family of techniques, which we will call "epitaxy-first" or "stacked-heterostructure" methods, involve first growing all of the epitaxial layers needed for both the optoelectronic devices and electronic devices on a suitable substrate. The top layers are then removed selectively in areas where devices are to be fabricated on lower layers and each of the various device types is formed in the appropriate layers. In variations on this idea, some of the epitaxial layers are grown, they are etched away where they will not be needed, and more epitaxial layers are grown in newly cleared areas; this approach results in a more planar surface but the growth and processing are much more complex. An important problem with the epitaxy-first approach is that pursuing it involves simultaneous development of sophisticated technologies for optoelectronic devices and integrated circuits. The task is enormous and as a practical matter only small scale OEICs have been demonstrated following this approach.
While the integration levels of epitaxy-first III-V OEICs have remained low, the degree of integration in commercial GaAs electronic (MESFET) integrated circuits has reached VLSI levels in recent years, and the technologies used in this integration use only refractory metals in contact with the semiconductor, and use Si IC upper-level interconnect and passivation technologies. These advances offer a route to achieving much higher levels of optoelectronic integration through epitaxial growth of III-V heterostructures on GaAs-based VLSI electronics as illustrated in Figure 1. This is essentially the GaAs-on-Si idea without the myriad of materials problems inherent in growing the III-Vs on silicon, and with all the advantages of building on a commercial integrated electronics foundation. This approach, which is called epitaxy-on-electronics (epi-on-electronics, for short), is described in detail in the section Epitaxy-on-Electronics Optoelectronic Integration. We feel that it offers the best promise for realizing high density, high perfomance optoelectronic integrated circuits.