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*******************************************************************************/
/* Behavioural components instantiated:
C_REG_FD_V7_0
C_GATE_BIT_V7_0
C_DIST_MEM_V7_0
C_SHIFT_FD_V7_0
C_ADDSUB_V7_0
*/
`timescale 1ns/1ps
![[Up: dds_sample dds1]](v2html-up.gif)
module dds_8bit
(
DATA,
WE,
A,
CLK,
CE,
RDY,
SINE,
COSINE
); // synthesis black_box
input [20 : 0] DATA;
input WE;
input [4 : 0] A;
input CLK;
input CE;
output RDY;
output [7 : 0] SINE;
output [7 : 0] COSINE;
//synopsys translate_off
wire n0 = 1'b0;
wire n1 = 1'b1;
wire n2;
wire n3;
wire n4;
wire n5;
wire n6;
wire n7;
wire n8;
wire n19;
wire n20;
wire n21;
wire n22;
wire n23;
wire n24;
wire n25;
wire n26;
wire n27;
wire n28;
wire n29;
wire n30;
wire n31;
wire n32;
wire n33;
wire n34;
wire n35;
wire n36;
wire n37;
wire n38;
wire n39;
wire n40;
wire n41;
wire n42;
wire n43;
wire n44;
wire n45;
wire n46;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n95;
wire n96;
wire n97;
wire n98;
wire n99;
wire n100;
wire n101;
wire n102;
wire n109;
wire n110;
wire n111;
wire n112;
wire n113;
wire n114;
wire n115;
wire n116;
wire n117;
wire n118;
wire n119;
wire n120;
wire n121;
wire n122;
wire n123;
wire n124;
wire n125;
wire n126;
wire n127;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n795;
wire n796;
wire n797;
wire n798;
wire n799;
wire n800;
wire n801;
wire n802;
wire n803;
wire n804;
wire n805;
wire n806;
wire n845;
wire n846;
wire n847;
wire n848;
wire n849;
wire n850;
wire n851;
wire n852;
wire n853;
wire n854;
wire n855;
wire n896;
wire n897;
wire n898;
wire n899;
wire n900;
wire n901;
wire n902;
wire n903;
wire n904;
wire n905;
wire n906;
wire n907;
wire n908;
wire n909;
wire n910;
wire n911;
wire n912;
wire n913;
wire n914;
wire n951;
wire n952;
wire n953;
wire n954;
wire n955;
wire n956;
wire n957;
wire n958;
wire n959;
wire n960;
wire n961;
wire n1004;
wire n1005;
wire n1006;
wire n1007;
wire n1008;
wire n1009;
wire n1010;
wire n1011;
wire n1012;
wire n1648;
wire n1649;
wire n1650;
wire n1651;
wire n1652;
wire n1653;
wire n1654;
wire n1659;
wire n1660;
wire n1661;
wire n1662;
wire n1663;
wire n1664;
wire n1665;
wire n1666;
wire n1684;
assign n82 = DATA[0];
assign n83 = DATA[1];
assign n84 = DATA[2];
assign n85 = DATA[3];
assign n86 = DATA[4];
assign n87 = DATA[5];
assign n88 = DATA[6];
assign n89 = DATA[7];
assign n90 = DATA[8];
assign n91 = DATA[9];
assign n92 = DATA[10];
assign n93 = DATA[11];
assign n94 = DATA[12];
assign n95 = DATA[13];
assign n96 = DATA[14];
assign n97 = DATA[15];
assign n98 = DATA[16];
assign n99 = DATA[17];
assign n100 = DATA[18];
assign n101 = DATA[19];
assign n102 = DATA[20];
assign n8 = WE;
assign n3 = A[0];
assign n4 = A[1];
assign n5 = A[2];
assign n6 = A[3];
assign n7 = A[4];
assign n109 = CLK;
assign n110 = CE;
assign RDY = n111;
assign SINE[0] = n112;
assign SINE[1] = n113;
assign SINE[2] = n114;
assign SINE[3] = n115;
assign SINE[4] = n116;
assign SINE[5] = n117;
assign SINE[6] = n118;
assign SINE[7] = n119;
assign COSINE[0] = n120;
assign COSINE[1] = n121;
assign COSINE[2] = n122;
assign COSINE[3] = n123;
assign COSINE[4] = n124;
assign COSINE[5] = n125;
assign COSINE[6] = n126;
assign COSINE[7] = n127;
wire [5 : 0] BU2_I;
assign BU2_I[0] = n3;
assign BU2_I[1] = n4;
assign BU2_I[2] = n5;
assign BU2_I[3] = n6;
assign BU2_I[4] = n7;
assign BU2_I[5] = n8;
wire BU2_T;
assign BU2_T = 1'b0;
wire BU2_EN;
assign BU2_EN = 1'b0;
wire BU2_Q;
wire BU2_CLK;
assign BU2_CLK = 1'b0;
wire BU2_CE;
assign BU2_CE = 1'b0;
wire BU2_ACLR;
assign BU2_ACLR = 1'b0;
wire BU2_ASET;
assign BU2_ASET = 1'b0;
wire BU2_AINIT;
assign BU2_AINIT = 1'b0;
wire BU2_SCLR;
assign BU2_SCLR = 1'b0;
wire BU2_SSET;
assign BU2_SSET = 1'b0;
wire BU2_SINIT;
assign BU2_SINIT = 1'b0;
wire BU2_O;
assign n2 = BU2_O;
C_GATE_BIT_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_gate_type*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_ce*/,
1 /* c_has_o*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
6 /* c_inputs*/,
"011111" /* c_input_inv_mask*/,
0 /* c_pipe_stages*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
1 /* c_sync_priority*/
)
BU2(
.I(BU2_I),
.T(BU2_T),
.EN(BU2_EN),
.Q(BU2_Q),
.CLK(BU2_CLK),
.CE(BU2_CE),
.ACLR(BU2_ACLR),
.ASET(BU2_ASET),
.AINIT(BU2_AINIT),
.SCLR(BU2_SCLR),
.SSET(BU2_SSET),
.SINIT(BU2_SINIT),
.O(BU2_O)
);
wire [20 : 0] BU12_D;
assign BU12_D[0] = n82;
assign BU12_D[1] = n83;
assign BU12_D[2] = n84;
assign BU12_D[3] = n85;
assign BU12_D[4] = n86;
assign BU12_D[5] = n87;
assign BU12_D[6] = n88;
assign BU12_D[7] = n89;
assign BU12_D[8] = n90;
assign BU12_D[9] = n91;
assign BU12_D[10] = n92;
assign BU12_D[11] = n93;
assign BU12_D[12] = n94;
assign BU12_D[13] = n95;
assign BU12_D[14] = n96;
assign BU12_D[15] = n97;
assign BU12_D[16] = n98;
assign BU12_D[17] = n99;
assign BU12_D[18] = n100;
assign BU12_D[19] = n101;
assign BU12_D[20] = n102;
wire [20 : 0] BU12_Q;
assign n173 = BU12_Q[0];
assign n174 = BU12_Q[1];
assign n175 = BU12_Q[2];
assign n176 = BU12_Q[3];
assign n177 = BU12_Q[4];
assign n178 = BU12_Q[5];
assign n179 = BU12_Q[6];
assign n180 = BU12_Q[7];
assign n181 = BU12_Q[8];
assign n182 = BU12_Q[9];
assign n183 = BU12_Q[10];
assign n184 = BU12_Q[11];
assign n185 = BU12_Q[12];
assign n186 = BU12_Q[13];
assign n187 = BU12_Q[14];
assign n188 = BU12_Q[15];
assign n189 = BU12_Q[16];
assign n190 = BU12_Q[17];
assign n191 = BU12_Q[18];
assign n192 = BU12_Q[19];
assign n193 = BU12_Q[20];
wire BU12_CLK;
assign BU12_CLK = n109;
wire BU12_CE;
assign BU12_CE = n2;
C_REG_FD_V7_0 #(
"000000000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"000000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
21 /* c_width*/
)
BU12(
.D(BU12_D),
.Q(BU12_Q),
.CLK(BU12_CLK),
.CE(BU12_CE)
);
wire [20 : 0] BU56_A;
assign BU56_A[0] = n19;
assign BU56_A[1] = n20;
assign BU56_A[2] = n21;
assign BU56_A[3] = n22;
assign BU56_A[4] = n23;
assign BU56_A[5] = n24;
assign BU56_A[6] = n25;
assign BU56_A[7] = n26;
assign BU56_A[8] = n27;
assign BU56_A[9] = n28;
assign BU56_A[10] = n29;
assign BU56_A[11] = n30;
assign BU56_A[12] = n31;
assign BU56_A[13] = n32;
assign BU56_A[14] = n33;
assign BU56_A[15] = n34;
assign BU56_A[16] = n35;
assign BU56_A[17] = n36;
assign BU56_A[18] = n37;
assign BU56_A[19] = n38;
assign BU56_A[20] = n39;
wire [20 : 0] BU56_B;
assign BU56_B[0] = n173;
assign BU56_B[1] = n174;
assign BU56_B[2] = n175;
assign BU56_B[3] = n176;
assign BU56_B[4] = n177;
assign BU56_B[5] = n178;
assign BU56_B[6] = n179;
assign BU56_B[7] = n180;
assign BU56_B[8] = n181;
assign BU56_B[9] = n182;
assign BU56_B[10] = n183;
assign BU56_B[11] = n184;
assign BU56_B[12] = n185;
assign BU56_B[13] = n186;
assign BU56_B[14] = n187;
assign BU56_B[15] = n188;
assign BU56_B[16] = n189;
assign BU56_B[17] = n190;
assign BU56_B[18] = n191;
assign BU56_B[19] = n192;
assign BU56_B[20] = n193;
wire [20 : 0] BU56_Q;
assign n19 = BU56_Q[0];
assign n20 = BU56_Q[1];
assign n21 = BU56_Q[2];
assign n22 = BU56_Q[3];
assign n23 = BU56_Q[4];
assign n24 = BU56_Q[5];
assign n25 = BU56_Q[6];
assign n26 = BU56_Q[7];
assign n27 = BU56_Q[8];
assign n28 = BU56_Q[9];
assign n29 = BU56_Q[10];
assign n30 = BU56_Q[11];
assign n31 = BU56_Q[12];
assign n32 = BU56_Q[13];
assign n33 = BU56_Q[14];
assign n34 = BU56_Q[15];
assign n35 = BU56_Q[16];
assign n36 = BU56_Q[17];
assign n37 = BU56_Q[18];
assign n38 = BU56_Q[19];
assign n39 = BU56_Q[20];
wire BU56_CLK;
assign BU56_CLK = n109;
wire BU56_CE;
assign BU56_CE = n110;
C_ADDSUB_V7_0 #(
0 /* c_add_mode*/,
"000000000000000000000" /* c_ainit_val*/,
1 /* c_a_type*/,
21 /* c_a_width*/,
1 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
1 /* c_b_type*/,
"000000000000000000000" /* c_b_value*/,
21 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
0 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
20 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
21 /* c_out_width*/,
0 /* c_pipe_stages*/,
"000000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU56(
.A(BU56_A),
.B(BU56_B),
.Q(BU56_Q),
.CLK(BU56_CLK),
.CE(BU56_CE)
);
wire BU182_CLK;
assign BU182_CLK = n109;
wire BU182_SDOUT;
assign n40 = BU182_SDOUT;
wire BU182_CE;
assign BU182_CE = n110;
C_SHIFT_FD_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
1 /* c_fill_data*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_d*/,
0 /* c_has_lsb_2_msb*/,
0 /* c_has_q*/,
0 /* c_has_sclr*/,
0 /* c_has_sdin*/,
1 /* c_has_sdout*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
1 /* c_shift_type*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
1 /* c_sync_priority*/,
1 /* c_width*/
)
BU182(
.CLK(BU182_CLK),
.SDOUT(BU182_SDOUT),
.CE(BU182_CE)
);
wire [14 : 0] BU506_A;
assign BU506_A[0] = n25;
assign BU506_A[1] = n26;
assign BU506_A[2] = n27;
assign BU506_A[3] = n28;
assign BU506_A[4] = n29;
assign BU506_A[5] = n30;
assign BU506_A[6] = n31;
assign BU506_A[7] = n32;
assign BU506_A[8] = n33;
assign BU506_A[9] = n34;
assign BU506_A[10] = n35;
assign BU506_A[11] = n36;
assign BU506_A[12] = n37;
assign BU506_A[13] = n38;
assign BU506_A[14] = n39;
wire [9 : 0] BU506_B;
assign BU506_B[0] = n47;
assign BU506_B[1] = n48;
assign BU506_B[2] = n49;
assign BU506_B[3] = n50;
assign BU506_B[4] = n51;
assign BU506_B[5] = n52;
assign BU506_B[6] = n53;
assign BU506_B[7] = n54;
assign BU506_B[8] = n55;
assign BU506_B[9] = n56;
wire [5 : 0] BU506_Q;
assign n41 = BU506_Q[0];
assign n42 = BU506_Q[1];
assign n43 = BU506_Q[2];
assign n44 = BU506_Q[3];
assign n45 = BU506_Q[4];
assign n46 = BU506_Q[5];
wire BU506_CLK;
assign BU506_CLK = n109;
wire BU506_CE;
assign BU506_CE = n110;
C_ADDSUB_V7_0 #(
0 /* c_add_mode*/,
"000000" /* c_ainit_val*/,
1 /* c_a_type*/,
15 /* c_a_width*/,
1 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
0 /* c_b_type*/,
"000000000000000" /* c_b_value*/,
10 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
0 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
14 /* c_high_bit*/,
1 /* c_latency*/,
9 /* c_low_bit*/,
6 /* c_out_width*/,
0 /* c_pipe_stages*/,
"000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU506(
.A(BU506_A),
.B(BU506_B),
.Q(BU506_Q),
.CLK(BU506_CLK),
.CE(BU506_CE)
);
wire [8 : 0] BU445_A;
assign BU445_A[0] = n896;
assign BU445_A[1] = n897;
assign BU445_A[2] = n898;
assign BU445_A[3] = n899;
assign BU445_A[4] = n900;
assign BU445_A[5] = n901;
assign BU445_A[6] = n902;
assign BU445_A[7] = n903;
assign BU445_A[8] = n904;
wire [8 : 0] BU445_B;
assign BU445_B[0] = n1004;
assign BU445_B[1] = n1005;
assign BU445_B[2] = n1006;
assign BU445_B[3] = n1007;
assign BU445_B[4] = n1008;
assign BU445_B[5] = n1009;
assign BU445_B[6] = n1010;
assign BU445_B[7] = n1011;
assign BU445_B[8] = n1012;
wire [9 : 0] BU445_Q;
assign n47 = BU445_Q[0];
assign n48 = BU445_Q[1];
assign n49 = BU445_Q[2];
assign n50 = BU445_Q[3];
assign n51 = BU445_Q[4];
assign n52 = BU445_Q[5];
assign n53 = BU445_Q[6];
assign n54 = BU445_Q[7];
assign n55 = BU445_Q[8];
assign n56 = BU445_Q[9];
wire BU445_CLK;
assign BU445_CLK = n109;
wire BU445_CE;
assign BU445_CE = n110;
C_ADDSUB_V7_0 #(
0 /* c_add_mode*/,
"0000000000" /* c_ainit_val*/,
0 /* c_a_type*/,
9 /* c_a_width*/,
0 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
0 /* c_b_type*/,
"0000000000" /* c_b_value*/,
9 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
0 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
9 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
10 /* c_out_width*/,
0 /* c_pipe_stages*/,
"0000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU445(
.A(BU445_A),
.B(BU445_B),
.Q(BU445_Q),
.CLK(BU445_CLK),
.CE(BU445_CE)
);
wire [7 : 0] BU259_A;
assign BU259_A[0] = n795;
assign BU259_A[1] = n796;
assign BU259_A[2] = n797;
assign BU259_A[3] = n798;
assign BU259_A[4] = n799;
assign BU259_A[5] = n800;
assign BU259_A[6] = n801;
assign BU259_A[7] = n802;
wire [7 : 0] BU259_B;
assign BU259_B[0] = n845;
assign BU259_B[1] = n846;
assign BU259_B[2] = n847;
assign BU259_B[3] = n848;
assign BU259_B[4] = n849;
assign BU259_B[5] = n850;
assign BU259_B[6] = n851;
assign BU259_B[7] = n852;
wire [8 : 0] BU259_Q;
assign n896 = BU259_Q[0];
assign n897 = BU259_Q[1];
assign n898 = BU259_Q[2];
assign n899 = BU259_Q[3];
assign n900 = BU259_Q[4];
assign n901 = BU259_Q[5];
assign n902 = BU259_Q[6];
assign n903 = BU259_Q[7];
assign n904 = BU259_Q[8];
wire BU259_CLK;
assign BU259_CLK = n109;
wire BU259_CE;
assign BU259_CE = n110;
C_ADDSUB_V7_0 #(
0 /* c_add_mode*/,
"000000000" /* c_ainit_val*/,
0 /* c_a_type*/,
8 /* c_a_width*/,
0 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
0 /* c_b_type*/,
"000000000" /* c_b_value*/,
8 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
0 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
8 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
9 /* c_out_width*/,
0 /* c_pipe_stages*/,
"000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU259(
.A(BU259_A),
.B(BU259_B),
.Q(BU259_Q),
.CLK(BU259_CLK),
.CE(BU259_CE)
);
wire [3 : 0] BU190_I;
assign BU190_I[0] = n804;
assign BU190_I[1] = n805;
assign BU190_I[2] = n806;
assign BU190_I[3] = n802;
wire BU190_T;
assign BU190_T = 1'b0;
wire BU190_EN;
assign BU190_EN = 1'b0;
wire BU190_Q;
wire BU190_CLK;
assign BU190_CLK = 1'b0;
wire BU190_CE;
assign BU190_CE = 1'b0;
wire BU190_ACLR;
assign BU190_ACLR = 1'b0;
wire BU190_ASET;
assign BU190_ASET = 1'b0;
wire BU190_AINIT;
assign BU190_AINIT = 1'b0;
wire BU190_SCLR;
assign BU190_SCLR = 1'b0;
wire BU190_SSET;
assign BU190_SSET = 1'b0;
wire BU190_SINIT;
assign BU190_SINIT = 1'b0;
wire BU190_O;
assign n803 = BU190_O;
C_GATE_BIT_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
4 /* c_gate_type*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_ce*/,
1 /* c_has_o*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
4 /* c_inputs*/,
"0000" /* c_input_inv_mask*/,
0 /* c_pipe_stages*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
1 /* c_sync_priority*/
)
BU190(
.I(BU190_I),
.T(BU190_T),
.EN(BU190_EN),
.Q(BU190_Q),
.CLK(BU190_CLK),
.CE(BU190_CE),
.ACLR(BU190_ACLR),
.ASET(BU190_ASET),
.AINIT(BU190_AINIT),
.SCLR(BU190_SCLR),
.SSET(BU190_SSET),
.SINIT(BU190_SINIT),
.O(BU190_O)
);
wire BU195_CLK;
assign BU195_CLK = n109;
wire BU195_SDIN;
assign BU195_SDIN = n803;
wire [12 : 0] BU195_Q;
assign n804 = BU195_Q[0];
assign n805 = BU195_Q[2];
assign n806 = BU195_Q[3];
assign n795 = BU195_Q[5];
assign n796 = BU195_Q[6];
assign n797 = BU195_Q[7];
assign n798 = BU195_Q[8];
assign n799 = BU195_Q[9];
assign n800 = BU195_Q[10];
assign n801 = BU195_Q[11];
assign n802 = BU195_Q[12];
wire BU195_CE;
assign BU195_CE = n110;
C_SHIFT_FD_V7_0 #(
"1000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
5 /* c_fill_data*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_d*/,
0 /* c_has_lsb_2_msb*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
1 /* c_has_sdin*/,
0 /* c_has_sdout*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
0 /* c_shift_type*/,
"1000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
13 /* c_width*/
)
BU195(
.CLK(BU195_CLK),
.SDIN(BU195_SDIN),
.Q(BU195_Q),
.CE(BU195_CE)
);
wire [3 : 0] BU224_I;
assign BU224_I[0] = n854;
assign BU224_I[1] = n855;
assign BU224_I[2] = n848;
assign BU224_I[3] = n852;
wire BU224_T;
assign BU224_T = 1'b0;
wire BU224_EN;
assign BU224_EN = 1'b0;
wire BU224_Q;
wire BU224_CLK;
assign BU224_CLK = 1'b0;
wire BU224_CE;
assign BU224_CE = 1'b0;
wire BU224_ACLR;
assign BU224_ACLR = 1'b0;
wire BU224_ASET;
assign BU224_ASET = 1'b0;
wire BU224_AINIT;
assign BU224_AINIT = 1'b0;
wire BU224_SCLR;
assign BU224_SCLR = 1'b0;
wire BU224_SSET;
assign BU224_SSET = 1'b0;
wire BU224_SINIT;
assign BU224_SINIT = 1'b0;
wire BU224_O;
assign n853 = BU224_O;
C_GATE_BIT_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
4 /* c_gate_type*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_ce*/,
1 /* c_has_o*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
4 /* c_inputs*/,
"0000" /* c_input_inv_mask*/,
0 /* c_pipe_stages*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
1 /* c_sync_priority*/
)
| This page: |
Created: | Thu Dec 8 21:42:35 2005 |
| |
From: |
./dds_8bit.v |