BU224(
.I(BU224_I),
.T(BU224_T),
.EN(BU224_EN),
.Q(BU224_Q),
.CLK(BU224_CLK),
.CE(BU224_CE),
.ACLR(BU224_ACLR),
.ASET(BU224_ASET),
.AINIT(BU224_AINIT),
.SCLR(BU224_SCLR),
.SSET(BU224_SSET),
.SINIT(BU224_SINIT),
.O(BU224_O)
);
wire BU229_CLK;
assign BU229_CLK = n109;
wire BU229_SDIN;
assign BU229_SDIN = n853;
wire [13 : 0] BU229_Q;
assign n854 = BU229_Q[0];
assign n855 = BU229_Q[5];
assign n845 = BU229_Q[6];
assign n846 = BU229_Q[7];
assign n847 = BU229_Q[8];
assign n848 = BU229_Q[9];
assign n849 = BU229_Q[10];
assign n850 = BU229_Q[11];
assign n851 = BU229_Q[12];
assign n852 = BU229_Q[13];
wire BU229_CE;
assign BU229_CE = n110;
C_SHIFT_FD_V7_0 #(
"10000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
5 /* c_fill_data*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_d*/,
0 /* c_has_lsb_2_msb*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
1 /* c_has_sdin*/,
0 /* c_has_sdout*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
0 /* c_shift_type*/,
"10000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
14 /* c_width*/
)
BU229(
.CLK(BU229_CLK),
.SDIN(BU229_SDIN),
.Q(BU229_Q),
.CE(BU229_CE)
);
wire [7 : 0] BU391_A;
assign BU391_A[0] = n905;
assign BU391_A[1] = n906;
assign BU391_A[2] = n907;
assign BU391_A[3] = n908;
assign BU391_A[4] = n909;
assign BU391_A[5] = n910;
assign BU391_A[6] = n911;
assign BU391_A[7] = n912;
wire [7 : 0] BU391_B;
assign BU391_B[0] = n951;
assign BU391_B[1] = n952;
assign BU391_B[2] = n953;
assign BU391_B[3] = n954;
assign BU391_B[4] = n955;
assign BU391_B[5] = n956;
assign BU391_B[6] = n957;
assign BU391_B[7] = n958;
wire [8 : 0] BU391_Q;
assign n1004 = BU391_Q[0];
assign n1005 = BU391_Q[1];
assign n1006 = BU391_Q[2];
assign n1007 = BU391_Q[3];
assign n1008 = BU391_Q[4];
assign n1009 = BU391_Q[5];
assign n1010 = BU391_Q[6];
assign n1011 = BU391_Q[7];
assign n1012 = BU391_Q[8];
wire BU391_CLK;
assign BU391_CLK = n109;
wire BU391_CE;
assign BU391_CE = n110;
C_ADDSUB_V7_0 #(
0 /* c_add_mode*/,
"000000000" /* c_ainit_val*/,
0 /* c_a_type*/,
8 /* c_a_width*/,
0 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
0 /* c_b_type*/,
"000000000" /* c_b_value*/,
8 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
0 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
8 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
9 /* c_out_width*/,
0 /* c_pipe_stages*/,
"000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU391(
.A(BU391_A),
.B(BU391_B),
.Q(BU391_Q),
.CLK(BU391_CLK),
.CE(BU391_CE)
);
wire [1 : 0] BU314_I;
assign BU314_I[0] = n914;
assign BU314_I[1] = n912;
wire BU314_T;
assign BU314_T = 1'b0;
wire BU314_EN;
assign BU314_EN = 1'b0;
wire BU314_Q;
wire BU314_CLK;
assign BU314_CLK = 1'b0;
wire BU314_CE;
assign BU314_CE = 1'b0;
wire BU314_ACLR;
assign BU314_ACLR = 1'b0;
wire BU314_ASET;
assign BU314_ASET = 1'b0;
wire BU314_AINIT;
assign BU314_AINIT = 1'b0;
wire BU314_SCLR;
assign BU314_SCLR = 1'b0;
wire BU314_SSET;
assign BU314_SSET = 1'b0;
wire BU314_SINIT;
assign BU314_SINIT = 1'b0;
wire BU314_O;
assign n913 = BU314_O;
C_GATE_BIT_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
4 /* c_gate_type*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_ce*/,
1 /* c_has_o*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
2 /* c_inputs*/,
"00" /* c_input_inv_mask*/,
0 /* c_pipe_stages*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
1 /* c_sync_priority*/
)
BU314(
.I(BU314_I),
.T(BU314_T),
.EN(BU314_EN),
.Q(BU314_Q),
.CLK(BU314_CLK),
.CE(BU314_CE),
.ACLR(BU314_ACLR),
.ASET(BU314_ASET),
.AINIT(BU314_AINIT),
.SCLR(BU314_SCLR),
.SSET(BU314_SSET),
.SINIT(BU314_SINIT),
.O(BU314_O)
);
wire BU319_CLK;
assign BU319_CLK = n109;
wire BU319_SDIN;
assign BU319_SDIN = n913;
wire [14 : 0] BU319_Q;
assign n914 = BU319_Q[0];
assign n905 = BU319_Q[7];
assign n906 = BU319_Q[8];
assign n907 = BU319_Q[9];
assign n908 = BU319_Q[10];
assign n909 = BU319_Q[11];
assign n910 = BU319_Q[12];
assign n911 = BU319_Q[13];
assign n912 = BU319_Q[14];
wire BU319_CE;
assign BU319_CE = n110;
C_SHIFT_FD_V7_0 #(
"100000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
5 /* c_fill_data*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_d*/,
0 /* c_has_lsb_2_msb*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
1 /* c_has_sdin*/,
0 /* c_has_sdout*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
0 /* c_shift_type*/,
"100000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
15 /* c_width*/
)
BU319(
.CLK(BU319_CLK),
.SDIN(BU319_SDIN),
.Q(BU319_Q),
.CE(BU319_CE)
);
wire [3 : 0] BU352_I;
assign BU352_I[0] = n960;
assign BU352_I[1] = n961;
assign BU352_I[2] = n954;
assign BU352_I[3] = n958;
wire BU352_T;
assign BU352_T = 1'b0;
wire BU352_EN;
assign BU352_EN = 1'b0;
wire BU352_Q;
wire BU352_CLK;
assign BU352_CLK = 1'b0;
wire BU352_CE;
assign BU352_CE = 1'b0;
wire BU352_ACLR;
assign BU352_ACLR = 1'b0;
wire BU352_ASET;
assign BU352_ASET = 1'b0;
wire BU352_AINIT;
assign BU352_AINIT = 1'b0;
wire BU352_SCLR;
assign BU352_SCLR = 1'b0;
wire BU352_SSET;
assign BU352_SSET = 1'b0;
wire BU352_SINIT;
assign BU352_SINIT = 1'b0;
wire BU352_O;
assign n959 = BU352_O;
C_GATE_BIT_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
4 /* c_gate_type*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_ce*/,
1 /* c_has_o*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
4 /* c_inputs*/,
"0000" /* c_input_inv_mask*/,
0 /* c_pipe_stages*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
1 /* c_sync_priority*/
)
BU352(
.I(BU352_I),
.T(BU352_T),
.EN(BU352_EN),
.Q(BU352_Q),
.CLK(BU352_CLK),
.CE(BU352_CE),
.ACLR(BU352_ACLR),
.ASET(BU352_ASET),
.AINIT(BU352_AINIT),
.SCLR(BU352_SCLR),
.SSET(BU352_SSET),
.SINIT(BU352_SINIT),
.O(BU352_O)
);
wire BU357_CLK;
assign BU357_CLK = n109;
wire BU357_SDIN;
assign BU357_SDIN = n959;
wire [15 : 0] BU357_Q;
assign n960 = BU357_Q[0];
assign n961 = BU357_Q[2];
assign n951 = BU357_Q[8];
assign n952 = BU357_Q[9];
assign n953 = BU357_Q[10];
assign n954 = BU357_Q[11];
assign n955 = BU357_Q[12];
assign n956 = BU357_Q[13];
assign n957 = BU357_Q[14];
assign n958 = BU357_Q[15];
wire BU357_CE;
assign BU357_CE = n110;
C_SHIFT_FD_V7_0 #(
"1000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
5 /* c_fill_data*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_d*/,
0 /* c_has_lsb_2_msb*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
1 /* c_has_sdin*/,
0 /* c_has_sdout*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
0 /* c_shift_type*/,
"1000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
16 /* c_width*/
)
BU357(
.CLK(BU357_CLK),
.SDIN(BU357_SDIN),
.Q(BU357_Q),
.CE(BU357_CE)
);
wire [5 : 0] BU746_D;
assign BU746_D[0] = n41;
assign BU746_D[1] = n42;
assign BU746_D[2] = n43;
assign BU746_D[3] = n44;
assign BU746_D[4] = n45;
assign BU746_D[5] = n46;
wire [5 : 0] BU746_Q;
assign n1649 = BU746_Q[0];
assign n1650 = BU746_Q[1];
assign n1651 = BU746_Q[2];
assign n1652 = BU746_Q[3];
assign n1653 = BU746_Q[4];
assign n1654 = BU746_Q[5];
wire BU746_CLK;
assign BU746_CLK = n109;
wire BU746_CE;
assign BU746_CE = n110;
C_REG_FD_V7_0 #(
"000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
6 /* c_width*/
)
BU746(
.D(BU746_D),
.Q(BU746_Q),
.CLK(BU746_CLK),
.CE(BU746_CE)
);
wire [5 : 0] BU761_D;
assign BU761_D[0] = n41;
assign BU761_D[1] = n42;
assign BU761_D[2] = n43;
assign BU761_D[3] = n44;
assign BU761_D[4] = n45;
assign BU761_D[5] = n46;
wire [5 : 0] BU761_Q;
assign n1661 = BU761_Q[0];
assign n1662 = BU761_Q[1];
assign n1663 = BU761_Q[2];
assign n1664 = BU761_Q[3];
assign n1659 = BU761_Q[4];
assign n1660 = BU761_Q[5];
wire BU761_CLK;
assign BU761_CLK = n109;
wire BU761_CE;
assign BU761_CE = n110;
C_REG_FD_V7_0 #(
"000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
6 /* c_width*/
)
BU761(
.D(BU761_D),
.Q(BU761_Q),
.CLK(BU761_CLK),
.CE(BU761_CE)
);
defparam BU776.INIT = 'h5555;
wire BU776_I0;
assign BU776_I0 = n1659;
wire BU776_I1;
assign BU776_I1 = 1'b0;
wire BU776_I2;
assign BU776_I2 = 1'b0;
wire BU776_I3;
assign BU776_I3 = 1'b0;
wire BU776_O;
assign n1665 = BU776_O;
LUT4 BU776(
.I0(BU776_I0),
.I1(BU776_I1),
.I2(BU776_I2),
.I3(BU776_I3),
.O(BU776_O)
);
defparam BU778.INIT = 'h6666;
wire BU778_I0;
assign BU778_I0 = n1660;
wire BU778_I1;
assign BU778_I1 = n1659;
wire BU778_I2;
assign BU778_I2 = 1'b0;
wire BU778_I3;
assign BU778_I3 = 1'b0;
wire BU778_O;
assign n1666 = BU778_O;
LUT4 BU778(
.I0(BU778_I0),
.I1(BU778_I1),
.I2(BU778_I2),
.I3(BU778_I3),
.O(BU778_O)
);
wire [5 : 0] BU572_A;
assign BU572_A[0] = n1649;
assign BU572_A[1] = n1650;
assign BU572_A[2] = n1651;
assign BU572_A[3] = n1652;
assign BU572_A[4] = n1653;
assign BU572_A[5] = n1654;
wire BU572_CLK;
assign BU572_CLK = n109;
wire BU572_QSPO_CE;
assign BU572_QSPO_CE = n1648;
wire [7 : 0] BU572_QSPO;
assign n112 = BU572_QSPO[0];
assign n113 = BU572_QSPO[1];
assign n114 = BU572_QSPO[2];
assign n115 = BU572_QSPO[3];
assign n116 = BU572_QSPO[4];
assign n117 = BU572_QSPO[5];
assign n118 = BU572_QSPO[6];
assign n119 = BU572_QSPO[7];
C_DIST_MEM_V7_0 #(
6 /* c_addr_width*/,
"0" /* c_default_data*/,
2 /* c_default_data_radix*/,
64 /* c_depth*/,
0 /* c_enable_rlocs*/,
0 /* c_generate_mif*/,
1 /* c_has_clk*/,
0 /* c_has_d*/,
0 /* c_has_dpo*/,
0 /* c_has_dpra*/,
0 /* c_has_i_ce*/,
0 /* c_has_qdpo*/,
0 /* c_has_qdpo_ce*/,
0 /* c_has_qdpo_clk*/,
0 /* c_has_qdpo_rst*/,
0 /* c_has_qdpo_srst*/,
1 /* c_has_qspo*/,
1 /* c_has_qspo_ce*/,
0 /* c_has_qspo_rst*/,
0 /* c_has_qspo_srst*/,
0 /* c_has_rd_en*/,
0 /* c_has_spo*/,
0 /* c_has_spra*/,
0 /* c_has_we*/,
1 /* c_latency*/,
"dds_800khz_8bit_SINCOS_TABLE_TRIG_ROM.mif" /* c_mem_init_file*/,
0 /* c_mem_type*/,
0 /* c_mux_type*/,
1 /* c_qce_joined*/,
0 /* c_qualify_we*/,
1 /* c_read_mif*/,
0 /* c_reg_a_d_inputs*/,
0 /* c_reg_dpra_input*/,
0 /* c_sync_enable*/,
8 /* c_width*/
)
BU572(
.A(BU572_A),
.CLK(BU572_CLK),
.QSPO_CE(BU572_QSPO_CE),
.QSPO(BU572_QSPO)
);
wire [5 : 0] BU657_A;
assign BU657_A[0] = n1661;
assign BU657_A[1] = n1662;
assign BU657_A[2] = n1663;
assign BU657_A[3] = n1664;
assign BU657_A[4] = n1665;
assign BU657_A[5] = n1666;
wire BU657_CLK;
assign BU657_CLK = n109;
wire BU657_QSPO_CE;
assign BU657_QSPO_CE = n1648;
wire [7 : 0] BU657_QSPO;
assign n120 = BU657_QSPO[0];
assign n121 = BU657_QSPO[1];
assign n122 = BU657_QSPO[2];
assign n123 = BU657_QSPO[3];
assign n124 = BU657_QSPO[4];
assign n125 = BU657_QSPO[5];
assign n126 = BU657_QSPO[6];
assign n127 = BU657_QSPO[7];
C_DIST_MEM_V7_0 #(
6 /* c_addr_width*/,
"0" /* c_default_data*/,
2 /* c_default_data_radix*/,
64 /* c_depth*/,
0 /* c_enable_rlocs*/,
0 /* c_generate_mif*/,
1 /* c_has_clk*/,
0 /* c_has_d*/,
0 /* c_has_dpo*/,
0 /* c_has_dpra*/,
0 /* c_has_i_ce*/,
0 /* c_has_qdpo*/,
0 /* c_has_qdpo_ce*/,
0 /* c_has_qdpo_clk*/,
0 /* c_has_qdpo_rst*/,
0 /* c_has_qdpo_srst*/,
1 /* c_has_qspo*/,
1 /* c_has_qspo_ce*/,
0 /* c_has_qspo_rst*/,
0 /* c_has_qspo_srst*/,
0 /* c_has_rd_en*/,
0 /* c_has_spo*/,
0 /* c_has_spra*/,
0 /* c_has_we*/,
1 /* c_latency*/,
"dds_800khz_8bit_SINCOS_TABLE_TRIG_ROM.mif" /* c_mem_init_file*/,
0 /* c_mem_type*/,
0 /* c_mux_type*/,
1 /* c_qce_joined*/,
0 /* c_qualify_we*/,
1 /* c_read_mif*/,
0 /* c_reg_a_d_inputs*/,
0 /* c_reg_dpra_input*/,
0 /* c_sync_enable*/,
8 /* c_width*/
)
BU657(
.A(BU657_A),
.CLK(BU657_CLK),
.QSPO_CE(BU657_QSPO_CE),
.QSPO(BU657_QSPO)
);
wire BU781_CLK;
assign BU781_CLK = n109;
wire BU781_SDIN;
assign BU781_SDIN = n40;
wire [1 : 0] BU781_Q;
assign n111 = BU781_Q[0];
assign n1684 = BU781_Q[1];
wire BU781_CE;
assign BU781_CE = n110;
C_SHIFT_FD_V7_0 #(
"00" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
5 /* c_fill_data*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_d*/,
0 /* c_has_lsb_2_msb*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
1 /* c_has_sdin*/,
0 /* c_has_sdout*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
1 /* c_shift_type*/,
"00" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
2 /* c_width*/
)
BU781(
.CLK(BU781_CLK),
.SDIN(BU781_SDIN),
.Q(BU781_Q),
.CE(BU781_CE)
);
defparam BU788.INIT = 'h8888;
wire BU788_I0;
assign BU788_I0 = n110;
wire BU788_I1;
assign BU788_I1 = n1684;
wire BU788_I2;
assign BU788_I2 = 1'b0;
wire BU788_I3;
assign BU788_I3 = 1'b0;
wire BU788_O;
assign n1648 = BU788_O;
LUT4 BU788(
.I0(BU788_I0),
.I1(BU788_I1),
.I2(BU788_I2),
.I3(BU788_I3),
.O(BU788_O)
);
//synopsys translate_on
endmodule
| This page: |
Created: | Thu Dec 8 21:42:35 2005 |
| |
From: |
./dds_8bit.v |