Prev PageHierarchyFilesModulesSignalsTasksFunctionsHelp
ABCDEFHIJKLMNOPRSTUVWXY

Signals index

W
 wea : cmem : input
Connects down to:BLKMEMDP_V6_1:inst:WEA 
Connects up to:jtag2mem_6111:cmem1:ram_we 
 write_data : jtag2mem : output reg
Connects up to:jtag2mem_6111:j2m:write_data1 
 write_data : jtag2mem_6111 : wire
Connects down to:cmem:cmem1:dina 
 write_data1 : jtag2mem_6111 : wire
Connects down to:jtag2mem:j2m:write_data 
 write_data2 : jtag2mem_6111 : wire
X
 x : vga_disphex : input
 x : vga_dispstr : input
 xnew : debounce : reg
Y
 y : vga_disphex : input
 y : vga_dispstr : input
ABCDEFHIJKLMNOPRSTUVWXY
HierarchyFilesModulesSignalsTasksFunctionsHelp

This page: Created:Sun Dec 11 09:59:58 2005

Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).Help