6.111 Course Information
Students should feel comfortable using computers.
A rudimentary knowledge of electrical fundamentals (6.002, 6.071) is assumed.
As with all project courses the end-of-term cruch can be an issue, so it would be
unwise to take this course with another which also has a significant design project
due at the end of term.
6.111 is a 12 unit (3-7-2) course with a substantial laboratory component
(7 hours per week). The final six weeks -- 72 course hours -- of the semester
are devoted to the final project.
MWF 1p - 2p in 34-101. Lectures are not held on some Fridays and during the
last six weeks of the course so that you can focus on labs and the final project.
See the course calendar for a detailed schedule.
There is no required text for the course, but we recommend the following
book if you would like a more thorough treatment of the topics covered
R. H. Katz, G. Borriello
Contemporary Logic Design, 2nd ed.
Prentice Hall (ISBN 0201308576)
There are many good Verilog books; we strongly recommend that you have
access to one. Several Verilog books are available for in-lab checkout from the
Digital Instrument Room (38-601).
D. E. Thomas, P. R. Moorby
The Verilog Hardware Description Language, 5th ed.
Kluwer Academic Publishers (ISBN 1402070896)
Verilog HDL, 2nd ed.
Prentice Hall (ISBN 0130449113)
On-line versions of the handouts
(in PDF) can be found at this website.
There are no graded problem sets. Instead there are on-line
with answers you can use to test your understanding of the material
and prepare for the labs.
There is one 2-hour, closed-book quiz on Wed, November 2, 7:30 - 9:30
in 34-101. The questions will
be similar (perhaps identical!) to the
and will ask you to provide short, written answers and/or
If exceptional circumstances make it impossible to take
the quiz at the designated time, please contact the staff before the
quiz to see if other arrangements can be made. Requests for make-ups
after the quiz has been given are unlikely to be successful.
There is no final exam.
The 6.111 lab is located on the sixth floor of Building 38 (room 38-600).
During business hours you can enter via the lab doors from the Building 36
elevator lobby. After business hours the sixth floor entrance is locked and
alarmed you need to enter and leave on the fifth floor and take the internal
stairs up to the 6.111 lab. The usual hours of operation are
|0900||2345||Monday - Thursday|
stockroom closes @ 1725
stockroom closes @ 1715
These times are subject to change, particularly around holidays; check the signs near the lab entrance and
make your plans accordingly. The lab will be staffed by Teaching Assistants (TAs)
or Lab Aides (LAs) for some, but not all, of these hours.
Each student will be issued their own lab supplies including a protoboard,
a collection of components used in the assignments, a pair of scope probes,
a pair of analyzer probes, and some hand tools. While wiring and some debugging can
be done at home, most assignments require the use of an oscilloscope,
logic analyzer and other special equipment, all of which are available
in the lab. The FPGA Laboratory Kit can be found at each lab bench.
Additional equipment and parts may be checked out from the
Digital Instrument Room (38-601) from 0900 to 1730 Monday through Friday.
During other hours some, but not all, of this equipment is available from
the fifth floor Instrument Room (38-501).
Remember to put your name on anything that you build in
the laboratory and leave unattended, otherwise it may be gone when
you return. There are some lockers for the safe storage of your supplies along
the 6th floor entry corridor; to get one for the semester apply at the 6th
floor instrument room desk.
There are four lab assignments to be completed individually. For
each lab you will be asked to turn in a report in addition to
completing a checkoff with a TA. Checkoffs and reports are due
on Fridays in the 6.111 lab. There is a 20%/day late penalty for
work completed 1 to 5 working days after the due date. No credit
will be given for unexcused lateness exceeding 5 days.
Note that each lab has multiple, often substantial, tasks you need
to complete and it is unlikely that you'll be able to complete the work
in one sitting (eg, the day the lab is due). The lab and TAs are very
busy just before an assignment is due so please plan accordingly.
6.111 is one of the courses which satisfies the EECS Communication-Intensive (CI-M)
third-year class requirement. Even if you have satisfied the requirement
in some other way, you will need to prepare a report and its
revision as described below.
The writing department will provide feedback on the first version of
your Lab 2 report. You are required to submit a revised version which
will then be assigned a final grade by the writing department; this grade
will contribute 10% to your final grade in 6.111. The 6.111 staff will
also evaluate this report for technical merit and assign a grade; this
grade will contribute another 5% to your final grade.
The Final Project is the most important assignment -- you'll get to
design an implement a small digital system of your own choosing, working
with one or at most two partners. The last six weeks of the term are devoted
exclusively to working on the project and its accompanying report.
We'll be providing lots of information
about the project as the term progresses, but here's a quick list of the
- choosing your partner(s) (10/24)
- project abstract (10/31)
- project proposal conference (11/4)
- project block diagram conference (11/11)
- project design presentations (11/14, 11/15, 11/16)
- project checklist (11/18)
- project demos and videotaping (12/12, 12/13, 12/14)
- project report due (12/14)
The Departmental Guidelines Relating to Academic Honesty require that
we inform you of our expectations regarding permissible academic
The labs should be done individually. You are welcome to get help from others
but the work you hand in must be your own.
Copying another person's work or allowing
your work to be copied by others is a serious academic offense and
will be treated as such by the course staff.
The final grade is determined by your performance on the quizzes, labs,
and final project:
- Quiz: 20%
- Lab 1: 5%
- Lab 2: 5%
- Lab 2 revised written report (CI-M): 10%
- Lab 3: 10%
- Lab 4: 10%
- Final project: 40%
- Quality and organization of presentation and report: 10%
- Complexity, innovation and risk: 10%
- Problem definition: 2%
- Architecture: 3%
- Design (modularity, Verilog): 5%
- Functionality: 10%
We construct a histogram of these summary numbers and proceed to
discuss the individual performance of each student. Some of the factors
- Diligence as measured by the time spent in the lab and attendance at
the Project Design Presentations.
- Completion of all the labs. It is extremely rare for a student to
receive an "A" without completing the labs. Of course, it is possible to
get a grade lower than "A" even if the labs are complete.
- Performance on the final project:
- Students who do not construct a final project or turn in a final report
will receive an "F".
- Project complexity is an important factor is discriminating between an "A"
and a "B". An "A" is rarely given if the final project is not at least
as complex as Labs 3 or 4.
Traditionally, the average performance (and hence grade) has been quite high
in 6.111. A large number of students do "A" level work and are, indeed, rewarded
with a grade of "A". The corollary to this is that, since average performance
levels are so high, punting any part of the subject can lead to a disappointing
grade. It's very important to keep up with the work.
Incompletes will not be given.