Prev PageHierarchyFilesModulesSignalsTasksFunctionsHelp
ABCDFIKLMNOPRSTUVWX

Signals index

C
 CE : dds_8bit : input
Connects up to:dds_sample:dds1:clk_dds 
 char_index : display_16hex : reg
 clean : debounce : output reg
Connects up to:dds_sample:dbreset:user_reset , user_updown3:dbu:up , user_updown3:dbd:down 
 CLK : dds_8bit : input
Connects up to:dds_sample:dds1:clk 
 clk : dds_sample : wire (used in @posedge)
Connects down to:BUFG:vclk2:O , SRL16:reset_sr:CLK , debounce:dbreset:clk , dds_8bit:dds1:CLK , audio:myaudio:clock_27mhz , tone750hz:tone:clock , user_updown3:uud1:clk , display_16hex:d1:clock_27mhz 
 clk : debounce : input (used in @posedge)
Connects up to:dds_sample:dbreset:clk , user_updown3:dbu:clk , user_updown3:dbd:clk 
 clk : user_updown3 : input (used in @posedge)
Connects down to:debounce:dbu:clk , debounce:dbd:clk 
Connects up to:dds_sample:uud1:clk 
 clk_dds : dds_sample : reg
Connects down to:dds_8bit:dds1:CE 
 clock : ac97commands : input (used in @posedge)
Connects up to:audio:cmds:clock_27mhz 
 clock : display_16hex : wire
 clock : tone750hz : input (used in @posedge)
Connects up to:dds_sample:tone:clk 
 clock1 : dds_sample : input
 clock2 : dds_sample : input
 clock_27mhz : audio : input (used in @posedge)
Connects down to:ac97commands:cmds:clock 
Connects up to:dds_sample:myaudio:clk 
 clock_27mhz : dds_sample : input
Connects down to:BUFG:vclk2:I 
 clock_27mhz : display_16hex : input (used in @posedge)
Connects up to:dds_sample:d1:clk 
 clock_feedback_in : dds_sample : input
 clock_feedback_out : dds_sample : output
 clock_tick : display_16hex : wire
 command : ac97commands : reg
 command_address : ac97 : input
Connects up to:audio:ac97:command_address 
 command_address : ac97commands : output
Connects up to:audio:cmds:command_address 
 command_address : audio : wire
Connects down to:ac97:ac97:command_address , ac97commands:cmds:command_address 
 command_data : ac97 : input
Connects up to:audio:ac97:command_data 
 command_data : ac97commands : output
Connects up to:audio:cmds:command_data 
 command_data : audio : wire
Connects down to:ac97:ac97:command_data , ac97commands:cmds:command_data 
 command_valid : ac97 : input
Connects up to:audio:ac97:command_valid 
 command_valid : ac97commands : output reg
Connects up to:audio:cmds:command_valid 
 command_valid : audio : wire
Connects down to:ac97:ac97:command_valid , ac97commands:cmds:command_valid 
 control : display_16hex : reg
 COSINE : dds_8bit : output
Connects up to:dds_sample:dds1:cosine 
 cosine : dds_sample : wire
Connects down to:dds_8bit:dds1:COSINE 
 count : debounce : reg
 count : display_16hex : reg
D
 DATA : dds_8bit : input
Connects up to:dds_sample:dds1:freq 
 data : dds_sample : wire
Connects down to:user_updown3:uud1:data 
 data : display_16hex : reg
 data : user_updown3 : output reg
Connects up to:dds_sample:uud1:data 
 data_in : display_16hex : input
Connects up to:dds_sample:d1:dispdata 
 daughtercard : dds_sample : inout
 dds_a : dds_sample : wire
Connects down to:dds_8bit:dds1:A 
 digselect : dds_sample : wire
Connects down to:user_updown3:uud1:incidx 
 dispdata : dds_sample : wire
Connects down to:display_16hex:d1:data_in 
 disp_blank : dds_sample : output
Connects down to:display_16hex:d1:disp_blank 
 disp_blank : display_16hex : output
Connects up to:dds_sample:d1:disp_blank 
 disp_ce_b : dds_sample : output
Connects down to:display_16hex:d1:disp_ce_b 
 disp_ce_b : display_16hex : output reg
Connects up to:dds_sample:d1:disp_ce_b 
 disp_clock : dds_sample : output
Connects down to:display_16hex:d1:disp_clock 
 disp_clock : display_16hex : output
Connects up to:dds_sample:d1:disp_clock 
 disp_data_in : dds_sample : input
 disp_data_out : dds_sample : output
Connects down to:display_16hex:d1:disp_data_out 
 disp_data_out : display_16hex : output reg
Connects up to:dds_sample:d1:disp_data_out 
 disp_reset_b : dds_sample : output
Connects down to:display_16hex:d1:disp_reset_b 
 disp_reset_b : display_16hex : output reg
Connects up to:dds_sample:d1:disp_reset_b 
 disp_rs : dds_sample : output
Connects down to:display_16hex:d1:disp_rs 
 disp_rs : display_16hex : output reg
Connects up to:dds_sample:d1:disp_rs 
 done : ac97commands : reg
 dots : display_16hex : reg
 dot_index : display_16hex : reg
 down : user_updown3 : wire
Connects down to:debounce:dbd:clean 
 dreset : display_16hex : wire
 dx : user_updown3 : wire
ABCDFIKLMNOPRSTUVWX
Next PageHierarchyFilesModulesSignalsTasksFunctionsHelp
This page: Created:Thu Dec 8 21:42:35 2005
Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).Help