assign BU273_dina[10] = 1'b0;
assign BU273_dina[9] = 1'b0;
assign BU273_dina[8] = 1'b0;
assign BU273_dina[7] = 1'b0;
assign BU273_dina[6] = 1'b0;
assign BU273_dina[5] = 1'b0;
assign BU273_dina[4] = 1'b0;
assign BU273_dina[3] = 1'b0;
assign BU273_dina[2] = 1'b0;
assign BU273_dina[1] = 1'b0;
assign BU273_dina[0] = 1'b0;
wire [16 : 0] BU273_dinb;
assign BU273_dinb[16] = 1'b0;
assign BU273_dinb[15] = 1'b0;
assign BU273_dinb[14] = 1'b0;
assign BU273_dinb[13] = 1'b0;
assign BU273_dinb[12] = 1'b0;
assign BU273_dinb[11] = 1'b0;
assign BU273_dinb[10] = 1'b0;
assign BU273_dinb[9] = 1'b0;
assign BU273_dinb[8] = 1'b0;
assign BU273_dinb[7] = 1'b0;
assign BU273_dinb[6] = 1'b0;
assign BU273_dinb[5] = 1'b0;
assign BU273_dinb[4] = 1'b0;
assign BU273_dinb[3] = 1'b0;
assign BU273_dinb[2] = 1'b0;
assign BU273_dinb[1] = 1'b0;
assign BU273_dinb[0] = 1'b0;
wire [16 : 0] BU273_douta;
assign n1540 = BU273_douta[16];
assign n1539 = BU273_douta[15];
assign n1538 = BU273_douta[14];
assign n1537 = BU273_douta[13];
assign n1536 = BU273_douta[12];
assign n1535 = BU273_douta[11];
assign n1534 = BU273_douta[10];
assign n1533 = BU273_douta[9];
assign n1532 = BU273_douta[8];
assign n1531 = BU273_douta[7];
assign n1530 = BU273_douta[6];
assign n1529 = BU273_douta[5];
assign n1528 = BU273_douta[4];
assign n1527 = BU273_douta[3];
assign n1526 = BU273_douta[2];
assign n1525 = BU273_douta[1];
assign n1524 = BU273_douta[0];
wire [16 : 0] BU273_doutb;
assign n1627 = BU273_doutb[16];
assign n1626 = BU273_doutb[15];
assign n1625 = BU273_doutb[14];
assign n1624 = BU273_doutb[13];
assign n1623 = BU273_doutb[12];
assign n1622 = BU273_doutb[11];
assign n1621 = BU273_doutb[10];
assign n1620 = BU273_doutb[9];
assign n1619 = BU273_doutb[8];
assign n1618 = BU273_doutb[7];
assign n1617 = BU273_doutb[6];
assign n1616 = BU273_doutb[5];
assign n1615 = BU273_doutb[4];
assign n1614 = BU273_doutb[3];
assign n1613 = BU273_doutb[2];
assign n1612 = BU273_doutb[1];
assign n1611 = BU273_doutb[0];
wire BU273_ena;
assign BU273_ena = n660;
wire BU273_enb;
assign BU273_enb = n660;
wire BU273_nda;
assign BU273_nda = 1'b0;
wire BU273_ndb;
assign BU273_ndb = 1'b0;
wire BU273_rfda;
wire BU273_rfdb;
wire BU273_rdya;
wire BU273_rdyb;
wire BU273_sinita;
assign BU273_sinita = 1'b0;
wire BU273_sinitb;
assign BU273_sinitb = 1'b0;
wire BU273_wea;
assign BU273_wea = 1'b0;
wire BU273_web;
assign BU273_web = 1'b0;
BLKMEMDP_V6_0 #(
10 /* c_addra_width*/,
10 /* c_addrb_width*/,
"0000" /* c_default_data*/,
1024 /* c_depth_a*/,
1024 /* c_depth_b*/,
0 /* c_enable_rlocs*/,
0 /* c_has_default_data*/,
0 /* c_has_dina*/,
0 /* c_has_dinb*/,
1 /* c_has_douta*/,
1 /* c_has_doutb*/,
1 /* c_has_ena*/,
1 /* c_has_enb*/,
0 /* c_has_limit_data_pitch*/,
0 /* c_has_nda*/,
0 /* c_has_ndb*/,
0 /* c_has_rdya*/,
0 /* c_has_rdyb*/,
0 /* c_has_rfda*/,
0 /* c_has_rfdb*/,
0 /* c_has_sinita*/,
0 /* c_has_sinitb*/,
0 /* c_has_wea*/,
0 /* c_has_web*/,
18 /* c_limit_data_pitch*/,
"dds_20bit_SINCOS_TABLE_TRIG_ROM.mif" /* c_mem_init_file*/,
1 /* c_pipe_stages_a*/,
1 /* c_pipe_stages_b*/,
0 /* c_reg_inputsa*/,
0 /* c_reg_inputsb*/,
"0000" /* c_sinita_value*/,
"0000" /* c_sinitb_value*/,
17 /* c_width_a*/,
17 /* c_width_b*/,
0 /* c_write_modea*/,
0 /* c_write_modeb*/,
"0" /* c_ybottom_addr*/,
1 /* c_yclka_is_rising*/,
1 /* c_yclkb_is_rising*/,
1 /* c_yena_is_high*/,
1 /* c_yenb_is_high*/,
"hierarchy1" /* c_yhierarchy*/,
0 /* c_ymake_bmm*/,
"4kx4" /* c_yprimitive_type*/,
1 /* c_ysinita_is_high*/,
1 /* c_ysinitb_is_high*/,
"1024" /* c_ytop_addr*/,
0 /* c_yuse_single_primitive*/,
1 /* c_ywea_is_high*/,
1 /* c_yweb_is_high*/,
1 /* c_yydisable_warnings*/
)
BU273(
.ADDRA(BU273_addra),
.ADDRB(BU273_addrb),
.CLKA(BU273_clka),
.CLKB(BU273_clkb),
.DINA(BU273_dina),
.DINB(BU273_dinb),
.DOUTA(BU273_douta),
.DOUTB(BU273_doutb),
.ENA(BU273_ena),
.ENB(BU273_enb),
.NDA(BU273_nda),
.NDB(BU273_ndb),
.RFDA(BU273_rfda),
.RFDB(BU273_rfdb),
.RDYA(BU273_rdya),
.RDYB(BU273_rdyb),
.SINITA(BU273_sinita),
.SINITB(BU273_sinitb),
.WEA(BU273_wea),
.WEB(BU273_web)
);
wire [17 : 0] BU735_A;
assign BU735_A[0] = 1'b0;
assign BU735_A[1] = 1'b0;
assign BU735_A[2] = 1'b0;
assign BU735_A[3] = 1'b0;
assign BU735_A[4] = 1'b0;
assign BU735_A[5] = 1'b0;
assign BU735_A[6] = 1'b0;
assign BU735_A[7] = 1'b0;
assign BU735_A[8] = 1'b0;
assign BU735_A[9] = 1'b0;
assign BU735_A[10] = 1'b0;
assign BU735_A[11] = 1'b0;
assign BU735_A[12] = 1'b0;
assign BU735_A[13] = 1'b0;
assign BU735_A[14] = 1'b0;
assign BU735_A[15] = 1'b0;
assign BU735_A[16] = 1'b0;
assign BU735_A[17] = 1'b0;
wire [17 : 0] BU735_B;
assign BU735_B[0] = n1524;
assign BU735_B[1] = n1525;
assign BU735_B[2] = n1526;
assign BU735_B[3] = n1527;
assign BU735_B[4] = n1528;
assign BU735_B[5] = n1529;
assign BU735_B[6] = n1530;
assign BU735_B[7] = n1531;
assign BU735_B[8] = n1532;
assign BU735_B[9] = n1533;
assign BU735_B[10] = n1534;
assign BU735_B[11] = n1535;
assign BU735_B[12] = n1536;
assign BU735_B[13] = n1537;
assign BU735_B[14] = n1538;
assign BU735_B[15] = n1539;
assign BU735_B[16] = n1540;
assign BU735_B[17] = n1519;
wire BU735_C_IN;
assign BU735_C_IN = n1523;
wire BU735_ADD;
assign BU735_ADD = n1522;
wire [17 : 0] BU735_Q;
assign n81 = BU735_Q[0];
assign n82 = BU735_Q[1];
assign n83 = BU735_Q[2];
assign n84 = BU735_Q[3];
assign n85 = BU735_Q[4];
assign n86 = BU735_Q[5];
assign n87 = BU735_Q[6];
assign n88 = BU735_Q[7];
assign n89 = BU735_Q[8];
assign n90 = BU735_Q[9];
assign n91 = BU735_Q[10];
assign n92 = BU735_Q[11];
assign n93 = BU735_Q[12];
assign n94 = BU735_Q[13];
assign n95 = BU735_Q[14];
assign n96 = BU735_Q[15];
assign n97 = BU735_Q[16];
assign n98 = BU735_Q[17];
wire BU735_CLK;
assign BU735_CLK = n659;
wire BU735_CE;
assign BU735_CE = n1646;
C_ADDSUB_V7_0 #(
2 /* c_add_mode*/,
"000000000000000000" /* c_ainit_val*/,
1 /* c_a_type*/,
18 /* c_a_width*/,
1 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
1 /* c_b_type*/,
"000000000000000000" /* c_b_value*/,
18 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
1 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
1 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
17 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
18 /* c_out_width*/,
0 /* c_pipe_stages*/,
"000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU735(
.A(BU735_A),
.B(BU735_B),
.C_IN(BU735_C_IN),
.ADD(BU735_ADD),
.Q(BU735_Q),
.CLK(BU735_CLK),
.CE(BU735_CE)
);
wire BU844_CLK;
assign BU844_CLK = n659;
wire [4 : 0] BU844_Q;
assign n99 = BU844_Q[0];
assign n1672 = BU844_Q[1];
wire BU844_CE;
assign BU844_CE = n660;
C_SHIFT_FD_V7_0 #(
"00000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
1 /* c_fill_data*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_d*/,
0 /* c_has_lsb_2_msb*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
0 /* c_has_sdin*/,
0 /* c_has_sdout*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
1 /* c_shift_type*/,
"00000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
5 /* c_width*/
)
BU844(
.CLK(BU844_CLK),
.Q(BU844_Q),
.CE(BU844_CE)
);
defparam BU857.INIT = 'h8888;
wire BU857_I0;
assign BU857_I0 = n660;
wire BU857_I1;
assign BU857_I1 = n1672;
wire BU857_I2;
assign BU857_I2 = 1'b0;
wire BU857_I3;
assign BU857_I3 = 1'b0;
wire BU857_O;
assign n1646 = BU857_O;
LUT4 BU857(
.I0(BU857_I0),
.I1(BU857_I1),
.I2(BU857_I2),
.I3(BU857_I3),
.O(BU857_O)
);
wire [17 : 0] BU860_A;
assign BU860_A[0] = 1'b0;
assign BU860_A[1] = 1'b0;
assign BU860_A[2] = 1'b0;
assign BU860_A[3] = 1'b0;
assign BU860_A[4] = 1'b0;
assign BU860_A[5] = 1'b0;
assign BU860_A[6] = 1'b0;
assign BU860_A[7] = 1'b0;
assign BU860_A[8] = 1'b0;
assign BU860_A[9] = 1'b0;
assign BU860_A[10] = 1'b0;
assign BU860_A[11] = 1'b0;
assign BU860_A[12] = 1'b0;
assign BU860_A[13] = 1'b0;
assign BU860_A[14] = 1'b0;
assign BU860_A[15] = 1'b0;
assign BU860_A[16] = 1'b0;
assign BU860_A[17] = 1'b0;
wire [17 : 0] BU860_B;
assign BU860_B[0] = n1611;
assign BU860_B[1] = n1612;
assign BU860_B[2] = n1613;
assign BU860_B[3] = n1614;
assign BU860_B[4] = n1615;
assign BU860_B[5] = n1616;
assign BU860_B[6] = n1617;
assign BU860_B[7] = n1618;
assign BU860_B[8] = n1619;
assign BU860_B[9] = n1620;
assign BU860_B[10] = n1621;
assign BU860_B[11] = n1622;
assign BU860_B[12] = n1623;
assign BU860_B[13] = n1624;
assign BU860_B[14] = n1625;
assign BU860_B[15] = n1626;
assign BU860_B[16] = n1627;
assign BU860_B[17] = n1606;
wire BU860_C_IN;
assign BU860_C_IN = n1610;
wire BU860_ADD;
assign BU860_ADD = n1609;
wire [17 : 0] BU860_Q;
assign n63 = BU860_Q[0];
assign n64 = BU860_Q[1];
assign n65 = BU860_Q[2];
assign n66 = BU860_Q[3];
assign n67 = BU860_Q[4];
assign n68 = BU860_Q[5];
assign n69 = BU860_Q[6];
assign n70 = BU860_Q[7];
assign n71 = BU860_Q[8];
assign n72 = BU860_Q[9];
assign n73 = BU860_Q[10];
assign n74 = BU860_Q[11];
assign n75 = BU860_Q[12];
assign n76 = BU860_Q[13];
assign n77 = BU860_Q[14];
assign n78 = BU860_Q[15];
assign n79 = BU860_Q[16];
assign n80 = BU860_Q[17];
wire BU860_CLK;
assign BU860_CLK = n659;
wire BU860_CE;
assign BU860_CE = n1646;
C_ADDSUB_V7_0 #(
2 /* c_add_mode*/,
"000000000000000000" /* c_ainit_val*/,
1 /* c_a_type*/,
18 /* c_a_width*/,
1 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
1 /* c_b_type*/,
"000000000000000000" /* c_b_value*/,
18 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
1 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
1 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
17 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
18 /* c_out_width*/,
0 /* c_pipe_stages*/,
"000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU860(
.A(BU860_A),
.B(BU860_B),
.C_IN(BU860_C_IN),
.ADD(BU860_ADD),
.Q(BU860_Q),
.CLK(BU860_CLK),
.CE(BU860_CE)
);
wire [17 : 0] BU1527_D;
assign BU1527_D[0] = n63;
assign BU1527_D[1] = n64;
assign BU1527_D[2] = n65;
assign BU1527_D[3] = n66;
assign BU1527_D[4] = n67;
assign BU1527_D[5] = n68;
assign BU1527_D[6] = n69;
assign BU1527_D[7] = n70;
assign BU1527_D[8] = n71;
assign BU1527_D[9] = n72;
assign BU1527_D[10] = n73;
assign BU1527_D[11] = n74;
assign BU1527_D[12] = n75;
assign BU1527_D[13] = n76;
assign BU1527_D[14] = n77;
assign BU1527_D[15] = n78;
assign BU1527_D[16] = n79;
assign BU1527_D[17] = n80;
wire [17 : 0] BU1527_Q;
assign n226 = BU1527_Q[0];
assign n227 = BU1527_Q[1];
assign n228 = BU1527_Q[2];
assign n229 = BU1527_Q[3];
assign n230 = BU1527_Q[4];
assign n231 = BU1527_Q[5];
assign n232 = BU1527_Q[6];
assign n233 = BU1527_Q[7];
assign n234 = BU1527_Q[8];
assign n235 = BU1527_Q[9];
assign n236 = BU1527_Q[10];
assign n237 = BU1527_Q[11];
assign n238 = BU1527_Q[12];
assign n239 = BU1527_Q[13];
assign n240 = BU1527_Q[14];
assign n241 = BU1527_Q[15];
assign n242 = BU1527_Q[16];
assign n243 = BU1527_Q[17];
wire BU1527_CLK;
assign BU1527_CLK = n659;
wire BU1527_CE;
assign BU1527_CE = n660;
C_REG_FD_V7_0 #(
"000000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
18 /* c_width*/
)
BU1527(
.D(BU1527_D),
.Q(BU1527_Q),
.CLK(BU1527_CLK),
.CE(BU1527_CE)
);
wire [16 : 0] BU1565_D;
assign BU1565_D[0] = n174;
assign BU1565_D[1] = n175;
assign BU1565_D[2] = n176;
assign BU1565_D[3] = n177;
assign BU1565_D[4] = n178;
assign BU1565_D[5] = n179;
assign BU1565_D[6] = n180;
assign BU1565_D[7] = n181;
assign BU1565_D[8] = n182;
assign BU1565_D[9] = n183;
assign BU1565_D[10] = n184;
assign BU1565_D[11] = n185;
assign BU1565_D[12] = n186;
assign BU1565_D[13] = n187;
assign BU1565_D[14] = n188;
assign BU1565_D[15] = n189;
assign BU1565_D[16] = n190;
wire [16 : 0] BU1565_Q;
assign n244 = BU1565_Q[0];
assign n245 = BU1565_Q[1];
assign n246 = BU1565_Q[2];
assign n247 = BU1565_Q[3];
assign n248 = BU1565_Q[4];
assign n249 = BU1565_Q[5];
assign n250 = BU1565_Q[6];
assign n251 = BU1565_Q[7];
assign n252 = BU1565_Q[8];
assign n253 = BU1565_Q[9];
assign n254 = BU1565_Q[10];
assign n255 = BU1565_Q[11];
assign n256 = BU1565_Q[12];
assign n257 = BU1565_Q[13];
assign n258 = BU1565_Q[14];
assign n259 = BU1565_Q[15];
assign n260 = BU1565_Q[16];
wire BU1565_CLK;
assign BU1565_CLK = n659;
wire BU1565_CE;
assign BU1565_CE = n660;
C_REG_FD_V7_0 #(
"00000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"00000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
17 /* c_width*/
)
BU1565(
.D(BU1565_D),
.Q(BU1565_Q),
.CLK(BU1565_CLK),
.CE(BU1565_CE)
);
wire [17 : 0] BU1728_D;
assign BU1728_D[0] = n81;
assign BU1728_D[1] = n82;
assign BU1728_D[2] = n83;
assign BU1728_D[3] = n84;
assign BU1728_D[4] = n85;
assign BU1728_D[5] = n86;
assign BU1728_D[6] = n87;
assign BU1728_D[7] = n88;
assign BU1728_D[8] = n89;
assign BU1728_D[9] = n90;
assign BU1728_D[10] = n91;
assign BU1728_D[11] = n92;
assign BU1728_D[12] = n93;
assign BU1728_D[13] = n94;
assign BU1728_D[14] = n95;
assign BU1728_D[15] = n96;
assign BU1728_D[16] = n97;
assign BU1728_D[17] = n98;
wire [17 : 0] BU1728_Q;
assign n296 = BU1728_Q[0];
assign n297 = BU1728_Q[1];
assign n298 = BU1728_Q[2];
assign n299 = BU1728_Q[3];
assign n300 = BU1728_Q[4];
assign n301 = BU1728_Q[5];
assign n302 = BU1728_Q[6];
assign n303 = BU1728_Q[7];
assign n304 = BU1728_Q[8];
assign n305 = BU1728_Q[9];
assign n306 = BU1728_Q[10];
assign n307 = BU1728_Q[11];
assign n308 = BU1728_Q[12];
assign n309 = BU1728_Q[13];
assign n310 = BU1728_Q[14];
assign n311 = BU1728_Q[15];
assign n312 = BU1728_Q[16];
assign n313 = BU1728_Q[17];
wire BU1728_CLK;
assign BU1728_CLK = n659;
wire BU1728_CE;
assign BU1728_CE = n660;
C_REG_FD_V7_0 #(
"000000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
18 /* c_width*/
)
BU1728(
.D(BU1728_D),
.Q(BU1728_Q),
.CLK(BU1728_CLK),
.CE(BU1728_CE)
);
wire [16 : 0] BU1766_D;
assign BU1766_D[0] = n174;
assign BU1766_D[1] = n175;
assign BU1766_D[2] = n176;
assign BU1766_D[3] = n177;
assign BU1766_D[4] = n178;
assign BU1766_D[5] = n179;
assign BU1766_D[6] = n180;
assign BU1766_D[7] = n181;
assign BU1766_D[8] = n182;
assign BU1766_D[9] = n183;
assign BU1766_D[10] = n184;
assign BU1766_D[11] = n185;
assign BU1766_D[12] = n186;
assign BU1766_D[13] = n187;
assign BU1766_D[14] = n188;
assign BU1766_D[15] = n189;
assign BU1766_D[16] = n190;
wire [16 : 0] BU1766_Q;
assign n314 = BU1766_Q[0];
assign n315 = BU1766_Q[1];
assign n316 = BU1766_Q[2];
assign n317 = BU1766_Q[3];
assign n318 = BU1766_Q[4];
assign n319 = BU1766_Q[5];
assign n320 = BU1766_Q[6];
assign n321 = BU1766_Q[7];
assign n322 = BU1766_Q[8];
assign n323 = BU1766_Q[9];
assign n324 = BU1766_Q[10];
assign n325 = BU1766_Q[11];
assign n326 = BU1766_Q[12];
assign n327 = BU1766_Q[13];
assign n328 = BU1766_Q[14];
assign n329 = BU1766_Q[15];
assign n330 = BU1766_Q[16];
wire BU1766_CLK;
assign BU1766_CLK = n659;
wire BU1766_CE;
assign BU1766_CE = n660;
C_REG_FD_V7_0 #(
"00000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"00000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
17 /* c_width*/
)
BU1766(
.D(BU1766_D),
.Q(BU1766_Q),
.CLK(BU1766_CLK),
.CE(BU1766_CE)
);
wire BU3184_CLK;
assign BU3184_CLK = n659;
wire BU3184_SDIN;
assign BU3184_SDIN = n99;
wire BU3184_SDOUT;
assign n620 = BU3184_SDOUT;
wire BU3184_CE;
assign BU3184_CE = n660;
C_SHIFT_FD_V7_0 #(
"0000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
5 /* c_fill_data*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_d*/,
0 /* c_has_lsb_2_msb*/,
0 /* c_has_q*/,
0 /* c_has_sclr*/,
1 /* c_has_sdin*/,
1 /* c_has_sdout*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
0 /* c_shift_type*/,
"0000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
7 /* c_width*/
)
BU3184(
.CLK(BU3184_CLK),
.SDIN(BU3184_SDIN),
.SDOUT(BU3184_SDOUT),
.CE(BU3184_CE)
);
defparam BU3204.INIT = 'h8888;
wire BU3204_I0;
assign BU3204_I0 = n660;
wire BU3204_I1;
assign BU3204_I1 = n620;
wire BU3204_I2;
assign BU3204_I2 = 1'b0;
wire BU3204_I3;
assign BU3204_I3 = 1'b0;
wire BU3204_O;
assign n331 = BU3204_O;
LUT4 BU3204(
.I0(BU3204_I0),
.I1(BU3204_I1),
.I2(BU3204_I2),
.I3(BU3204_I3),
.O(BU3204_O)
);
wire BU3205_D;
assign BU3205_D = n331;
wire BU3205_C;
assign BU3205_C = n659;
wire BU3205_CE;
assign BU3205_CE = n660;
wire BU3205_Q;
assign n661 = BU3205_Q;
FDE BU3205(
.D(BU3205_D),
.C(BU3205_C),
.CE(BU3205_CE),
.Q(BU3205_Q)
);
wire BU970_clk;
assign BU970_clk = n659;
wire [15 : 0] BU970_a;
assign BU970_a[15] = n38;
assign BU970_a[14] = n37;
assign BU970_a[13] = n36;
assign BU970_a[12] = n35;
assign BU970_a[11] = n34;
assign BU970_a[10] = n33;
assign BU970_a[9] = n32;
assign BU970_a[8] = n31;
assign BU970_a[7] = n30;
assign BU970_a[6] = n29;
assign BU970_a[5] = n28;
assign BU970_a[4] = n27;
assign BU970_a[3] = n26;
assign BU970_a[2] = n25;
assign BU970_a[1] = n24;
assign BU970_a[0] = n23;
wire [6 : 0] BU970_b;
assign BU970_b[6] = 1'b0;
assign BU970_b[5] = 1'b0;
assign BU970_b[4] = 1'b0;
assign BU970_b[3] = 1'b0;
assign BU970_b[2] = 1'b0;
assign BU970_b[1] = 1'b0;
assign BU970_b[0] = 1'b0;
wire [22 : 0] BU970_o;
wire [22 : 0] BU970_q;
assign n139 = BU970_q[22];
assign n138 = BU970_q[21];
assign n137 = BU970_q[20];
assign n136 = BU970_q[19];
assign n135 = BU970_q[18];
assign n134 = BU970_q[17];
assign n133 = BU970_q[16];
assign n132 = BU970_q[15];
wire BU970_a_signed;
assign BU970_a_signed = 1'b0;
wire BU970_loadb;
assign BU970_loadb = 1'b0;
wire BU970_load_done;
wire BU970_swapb;
assign BU970_swapb = 1'b0;
wire BU970_ce;
assign BU970_ce = n660;
wire BU970_aclr;
assign BU970_aclr = 1'b0;
wire BU970_sclr;
assign BU970_sclr = 1'b0;
wire BU970_rfd;
wire BU970_nd;
assign BU970_nd = 1'b0;
wire BU970_rdy;
MULT_GEN_V7_0 #(
8 /* bram_addr_width*/,
1 /* c_a_type*/,
16 /* c_a_width*/,
16 /* c_baat*/,
1 /* c_b_constant*/,
1 /* c_b_type*/,
"1100101" /* c_b_value*/,
7 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_a_signed*/,
1 /* c_has_b*/,
1 /* c_has_ce*/,
0 /* c_has_loadb*/,
0 /* c_has_load_done*/,
0 /* c_has_nd*/,
0 /* c_has_o*/,
1 /* c_has_q*/,
0 /* c_has_rdy*/,
0 /* c_has_rfd*/,
0 /* c_has_sclr*/,
0 /* c_has_swapb*/,
"mem" /* c_mem_init_prefix*/,
0 /* c_mem_type*/,
2 /* c_mult_type*/,
0 /* c_output_hold*/,
23 /* c_out_width*/,
1 /* c_pipeline*/,
0 /* c_reg_a_b_inputs*/,
0 /* c_sqm_type*/,
0 /* c_stack_adders*/,
0 /* c_standalone*/,
1 /* c_sync_enable*/,
1 /* c_use_luts*/,
0 /* c_v2_speed*/
)
BU970(
.CLK(BU970_clk),
.A(BU970_a),
.B(BU970_b),
.O(BU970_o),
.Q(BU970_q),
.A_SIGNED(BU970_a_signed),
.LOADB(BU970_loadb),
.LOAD_DONE(BU970_load_done),
.SWAPB(BU970_swapb),
.CE(BU970_ce),
.ACLR(BU970_aclr),
.SCLR(BU970_sclr),
.RFD(BU970_rfd),
.ND(BU970_nd),
.RDY(BU970_rdy)
);
wire BU1471_CLK;
assign BU1471_CLK = n659;
wire [16 : 0] BU1471_D;
assign BU1471_D[0] = n132;
assign BU1471_D[1] = n133;
assign BU1471_D[2] = n134;
assign BU1471_D[3] = n135;
assign BU1471_D[4] = n136;
assign BU1471_D[5] = n137;
assign BU1471_D[6] = n138;
assign BU1471_D[7] = n139;
assign BU1471_D[8] = 1'b0;
assign BU1471_D[9] = 1'b0;
assign BU1471_D[10] = 1'b0;
assign BU1471_D[11] = 1'b0;
assign BU1471_D[12] = 1'b0;
assign BU1471_D[13] = 1'b0;
assign BU1471_D[14] = 1'b0;
assign BU1471_D[15] = 1'b0;
assign BU1471_D[16] = 1'b0;
wire [16 : 0] BU1471_Q;
assign n174 = BU1471_Q[0];
assign n175 = BU1471_Q[1];
assign n176 = BU1471_Q[2];
assign n177 = BU1471_Q[3];
assign n178 = BU1471_Q[4];
assign n179 = BU1471_Q[5];
assign n180 = BU1471_Q[6];
assign n181 = BU1471_Q[7];
assign n182 = BU1471_Q[8];
assign n183 = BU1471_Q[9];
assign n184 = BU1471_Q[10];
assign n185 = BU1471_Q[11];
assign n186 = BU1471_Q[12];
assign n187 = BU1471_Q[13];
assign n188 = BU1471_Q[14];
assign n189 = BU1471_Q[15];
assign n190 = BU1471_Q[16];
wire BU1471_CE;
assign BU1471_CE = n660;
C_SHIFT_RAM_V7_0 #(
1 /* c_addr_width*/,
"00000000000000000" /* c_ainit_val*/,
"0" /* c_default_data*/,
2 /* c_default_data_radix*/,
2 /* c_depth*/,
0 /* c_enable_rlocs*/,
0 /* c_generate_mif*/,
0 /* c_has_a*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"null" /* c_mem_init_file*/,
2 /* c_mem_init_radix*/,
0 /* c_read_mif*/,
1 /* c_reg_last_bit*/,
0 /* c_shift_type*/,
"00000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
17 /* c_width*/
)
BU1471(
.CLK(BU1471_CLK),
.D(BU1471_D),
.Q(BU1471_Q),
.CE(BU1471_CE)
);
wire BU1601_clk;
assign BU1601_clk = n659;
wire [17 : 0] BU1601_a;
assign BU1601_a[17] = n243;
assign BU1601_a[16] = n242;
assign BU1601_a[15] = n241;
assign BU1601_a[14] = n240;
assign BU1601_a[13] = n239;
assign BU1601_a[12] = n238;
assign BU1601_a[11] = n237;
assign BU1601_a[10] = n236;
assign BU1601_a[9] = n235;
assign BU1601_a[8] = n234;
assign BU1601_a[7] = n233;
assign BU1601_a[6] = n232;
assign BU1601_a[5] = n231;
assign BU1601_a[4] = n230;
assign BU1601_a[3] = n229;
assign BU1601_a[2] = n228;
assign BU1601_a[1] = n227;
assign BU1601_a[0] = n226;
wire [16 : 0] BU1601_b;
assign BU1601_b[16] = n260;
assign BU1601_b[15] = n259;
assign BU1601_b[14] = n258;
assign BU1601_b[13] = n257;
assign BU1601_b[12] = n256;
assign BU1601_b[11] = n255;
assign BU1601_b[10] = n254;
assign BU1601_b[9] = n253;
assign BU1601_b[8] = n252;
assign BU1601_b[7] = n251;
assign BU1601_b[6] = n250;
assign BU1601_b[5] = n249;
assign BU1601_b[4] = n248;
assign BU1601_b[3] = n247;
assign BU1601_b[2] = n246;
assign BU1601_b[1] = n245;
assign BU1601_b[0] = n244;
wire [34 : 0] BU1601_o;
wire [34 : 0] BU1601_q;
assign n225 = BU1601_q[34];
assign n224 = BU1601_q[33];
assign n223 = BU1601_q[32];