wire BU2473_CLK;
assign BU2473_CLK = n659;
wire BU2473_CE;
assign BU2473_CE = n660;
C_REG_FD_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU2473(
.D(BU2473_D),
.Q(BU2473_Q),
.CLK(BU2473_CLK),
.CE(BU2473_CE)
);
wire [19 : 0] BU2333_A;
assign BU2333_A[0] = n6385;
assign BU2333_A[1] = n6386;
assign BU2333_A[2] = n6387;
assign BU2333_A[3] = n6388;
assign BU2333_A[4] = n6389;
assign BU2333_A[5] = n6390;
assign BU2333_A[6] = n6391;
assign BU2333_A[7] = n6392;
assign BU2333_A[8] = n6393;
assign BU2333_A[9] = n6394;
assign BU2333_A[10] = n6395;
assign BU2333_A[11] = n6396;
assign BU2333_A[12] = n6397;
assign BU2333_A[13] = n6398;
assign BU2333_A[14] = n6399;
assign BU2333_A[15] = n6400;
assign BU2333_A[16] = n6401;
assign BU2333_A[17] = n6402;
assign BU2333_A[18] = n6403;
assign BU2333_A[19] = n6404;
wire [0 : 0] BU2333_B;
assign BU2333_B[0] = n6428;
wire [20 : 0] BU2333_Q;
assign n6407 = BU2333_Q[0];
assign n6408 = BU2333_Q[1];
assign n6409 = BU2333_Q[2];
assign n6410 = BU2333_Q[3];
assign n6411 = BU2333_Q[4];
assign n6412 = BU2333_Q[5];
assign n6413 = BU2333_Q[6];
assign n6414 = BU2333_Q[7];
assign n6415 = BU2333_Q[8];
assign n6416 = BU2333_Q[9];
assign n6417 = BU2333_Q[10];
assign n6418 = BU2333_Q[11];
assign n6419 = BU2333_Q[12];
assign n6420 = BU2333_Q[13];
assign n6421 = BU2333_Q[14];
assign n6422 = BU2333_Q[15];
assign n6423 = BU2333_Q[16];
assign n6424 = BU2333_Q[17];
assign n6425 = BU2333_Q[18];
assign n6426 = BU2333_Q[19];
wire BU2333_CLK;
assign BU2333_CLK = n659;
wire BU2333_CE;
assign BU2333_CE = n660;
C_ADDSUB_V7_0 #(
0 /* c_add_mode*/,
"000000000000000000000" /* c_ainit_val*/,
0 /* c_a_type*/,
20 /* c_a_width*/,
0 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
1 /* c_b_type*/,
"000000000000000000000" /* c_b_value*/,
1 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
0 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
20 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
21 /* c_out_width*/,
0 /* c_pipe_stages*/,
"000000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU2333(
.A(BU2333_A),
.B(BU2333_B),
.Q(BU2333_Q),
.CLK(BU2333_CLK),
.CE(BU2333_CE)
);
defparam BU2477.INIT = 'h7340;
wire BU2477_I0;
assign BU2477_I0 = n6462;
wire BU2477_I1;
assign BU2477_I1 = n6461;
wire BU2477_I2;
assign BU2477_I2 = n660;
wire BU2477_I3;
assign BU2477_I3 = n6465;
wire BU2477_O;
assign n6464 = BU2477_O;
LUT4 BU2477(
.I0(BU2477_I0),
.I1(BU2477_I1),
.I2(BU2477_I2),
.I3(BU2477_I3),
.O(BU2477_O)
);
defparam BU2479.INIT = 'h0200;
wire BU2479_I0;
assign BU2479_I0 = n6462;
wire BU2479_I1;
assign BU2479_I1 = n6463;
wire BU2479_I2;
assign BU2479_I2 = n6426;
wire BU2479_I3;
assign BU2479_I3 = n660;
wire BU2479_O;
assign n6465 = BU2479_O;
LUT4 BU2479(
.I0(BU2479_I0),
.I1(BU2479_I1),
.I2(BU2479_I2),
.I3(BU2479_I3),
.O(BU2479_O)
);
defparam BU2481.INIT = 'ha040;
wire BU2481_I0;
assign BU2481_I0 = n6462;
wire BU2481_I1;
assign BU2481_I1 = n6426;
wire BU2481_I2;
assign BU2481_I2 = n660;
wire BU2481_I3;
assign BU2481_I3 = n6461;
wire BU2481_O;
assign n6467 = BU2481_O;
LUT4 BU2481(
.I0(BU2481_I0),
.I1(BU2481_I1),
.I2(BU2481_I2),
.I3(BU2481_I3),
.O(BU2481_O)
);
wire [18 : 0] BU2483_D;
assign BU2483_D[0] = n6407;
assign BU2483_D[1] = n6408;
assign BU2483_D[2] = n6409;
assign BU2483_D[3] = n6410;
assign BU2483_D[4] = n6411;
assign BU2483_D[5] = n6412;
assign BU2483_D[6] = n6413;
assign BU2483_D[7] = n6414;
assign BU2483_D[8] = n6415;
assign BU2483_D[9] = n6416;
assign BU2483_D[10] = n6417;
assign BU2483_D[11] = n6418;
assign BU2483_D[12] = n6419;
assign BU2483_D[13] = n6420;
assign BU2483_D[14] = n6421;
assign BU2483_D[15] = n6422;
assign BU2483_D[16] = n6423;
assign BU2483_D[17] = n6424;
assign BU2483_D[18] = n6425;
wire [18 : 0] BU2483_Q;
assign n580 = BU2483_Q[0];
assign n581 = BU2483_Q[1];
assign n582 = BU2483_Q[2];
assign n583 = BU2483_Q[3];
assign n584 = BU2483_Q[4];
assign n585 = BU2483_Q[5];
assign n586 = BU2483_Q[6];
assign n587 = BU2483_Q[7];
assign n588 = BU2483_Q[8];
assign n589 = BU2483_Q[9];
assign n590 = BU2483_Q[10];
assign n591 = BU2483_Q[11];
assign n592 = BU2483_Q[12];
assign n593 = BU2483_Q[13];
assign n594 = BU2483_Q[14];
assign n595 = BU2483_Q[15];
assign n596 = BU2483_Q[16];
assign n597 = BU2483_Q[17];
assign n598 = BU2483_Q[18];
wire BU2483_CLK;
assign BU2483_CLK = n659;
wire BU2483_CE;
assign BU2483_CE = n660;
wire BU2483_SCLR;
assign BU2483_SCLR = n6464;
wire BU2483_SSET;
assign BU2483_SSET = n6467;
C_REG_FD_V7_0 #(
"0000000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
1 /* c_has_sclr*/,
0 /* c_has_sinit*/,
1 /* c_has_sset*/,
"0000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
19 /* c_width*/
)
BU2483(
.D(BU2483_D),
.Q(BU2483_Q),
.CLK(BU2483_CLK),
.CE(BU2483_CE),
.SCLR(BU2483_SCLR),
.SSET(BU2483_SSET)
);
wire [0 : 0] BU2564_D;
assign BU2564_D[0] = n6426;
wire [0 : 0] BU2564_Q;
assign n599 = BU2564_Q[0];
wire BU2564_CLK;
assign BU2564_CLK = n659;
wire BU2564_CE;
assign BU2564_CE = n660;
wire BU2564_SCLR;
assign BU2564_SCLR = n6467;
wire BU2564_SSET;
assign BU2564_SSET = n6464;
C_REG_FD_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
1 /* c_has_sclr*/,
0 /* c_has_sinit*/,
1 /* c_has_sset*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU2564(
.D(BU2564_D),
.Q(BU2564_Q),
.CLK(BU2564_CLK),
.CE(BU2564_CE),
.SCLR(BU2564_SCLR),
.SSET(BU2564_SSET)
);
wire [0 : 0] BU2894_D;
assign BU2894_D[0] = n7246;
wire [0 : 0] BU2894_Q;
assign n7214 = BU2894_Q[0];
wire BU2894_CLK;
assign BU2894_CLK = n659;
wire BU2894_CE;
assign BU2894_CE = n660;
C_REG_FD_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU2894(
.D(BU2894_D),
.Q(BU2894_Q),
.CLK(BU2894_CLK),
.CE(BU2894_CE)
);
defparam BU2898.INIT = 'hc4c4;
wire BU2898_I0;
assign BU2898_I0 = n7190;
wire BU2898_I1;
assign BU2898_I1 = n557;
wire BU2898_I2;
assign BU2898_I2 = n7231;
wire BU2898_I3;
assign BU2898_I3 = 1'b0;
wire BU2898_O;
assign n7246 = BU2898_O;
LUT4 BU2898(
.I0(BU2898_I0),
.I1(BU2898_I1),
.I2(BU2898_I2),
.I3(BU2898_I3),
.O(BU2898_O)
);
wire [13 : 0] BU2875_I;
assign BU2875_I[0] = n543;
assign BU2875_I[1] = n544;
assign BU2875_I[2] = n545;
assign BU2875_I[3] = n546;
assign BU2875_I[4] = n547;
assign BU2875_I[5] = n548;
assign BU2875_I[6] = n549;
assign BU2875_I[7] = n550;
assign BU2875_I[8] = n551;
assign BU2875_I[9] = n552;
assign BU2875_I[10] = n553;
assign BU2875_I[11] = n554;
assign BU2875_I[12] = n555;
assign BU2875_I[13] = n556;
wire BU2875_T;
assign BU2875_T = 1'b0;
wire BU2875_EN;
assign BU2875_EN = 1'b0;
wire BU2875_Q;
wire BU2875_CLK;
assign BU2875_CLK = 1'b0;
wire BU2875_CE;
assign BU2875_CE = 1'b0;
wire BU2875_ACLR;
assign BU2875_ACLR = 1'b0;
wire BU2875_ASET;
assign BU2875_ASET = 1'b0;
wire BU2875_AINIT;
assign BU2875_AINIT = 1'b0;
wire BU2875_SCLR;
assign BU2875_SCLR = 1'b0;
wire BU2875_SSET;
assign BU2875_SSET = 1'b0;
wire BU2875_SINIT;
assign BU2875_SINIT = 1'b0;
wire BU2875_O;
assign n7231 = BU2875_O;
C_GATE_BIT_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
2 /* c_gate_type*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_ce*/,
1 /* c_has_o*/,
1 /* c_has_q*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
14 /* c_inputs*/,
"000000000000000" /* c_input_inv_mask*/,
0 /* c_pipe_stages*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
1 /* c_sync_priority*/
)
BU2875(
.I(BU2875_I),
.T(BU2875_T),
.EN(BU2875_EN),
.Q(BU2875_Q),
.CLK(BU2875_CLK),
.CE(BU2875_CE),
.ACLR(BU2875_ACLR),
.ASET(BU2875_ASET),
.AINIT(BU2875_AINIT),
.SCLR(BU2875_SCLR),
.SSET(BU2875_SSET),
.SINIT(BU2875_SINIT),
.O(BU2875_O)
);
wire [19 : 0] BU2834_D;
assign BU2834_D[0] = n558;
assign BU2834_D[1] = n559;
assign BU2834_D[2] = n560;
assign BU2834_D[3] = n561;
assign BU2834_D[4] = n562;
assign BU2834_D[5] = n563;
assign BU2834_D[6] = n564;
assign BU2834_D[7] = n565;
assign BU2834_D[8] = n566;
assign BU2834_D[9] = n567;
assign BU2834_D[10] = n568;
assign BU2834_D[11] = n569;
assign BU2834_D[12] = n570;
assign BU2834_D[13] = n571;
assign BU2834_D[14] = n572;
assign BU2834_D[15] = n573;
assign BU2834_D[16] = n574;
assign BU2834_D[17] = n575;
assign BU2834_D[18] = n576;
assign BU2834_D[19] = n577;
wire [19 : 0] BU2834_Q;
assign n7171 = BU2834_Q[0];
assign n7172 = BU2834_Q[1];
assign n7173 = BU2834_Q[2];
assign n7174 = BU2834_Q[3];
assign n7175 = BU2834_Q[4];
assign n7176 = BU2834_Q[5];
assign n7177 = BU2834_Q[6];
assign n7178 = BU2834_Q[7];
assign n7179 = BU2834_Q[8];
assign n7180 = BU2834_Q[9];
assign n7181 = BU2834_Q[10];
assign n7182 = BU2834_Q[11];
assign n7183 = BU2834_Q[12];
assign n7184 = BU2834_Q[13];
assign n7185 = BU2834_Q[14];
assign n7186 = BU2834_Q[15];
assign n7187 = BU2834_Q[16];
assign n7188 = BU2834_Q[17];
assign n7189 = BU2834_Q[18];
assign n7190 = BU2834_Q[19];
wire BU2834_CLK;
assign BU2834_CLK = n659;
wire BU2834_CE;
assign BU2834_CE = n660;
C_REG_FD_V7_0 #(
"00000000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"00000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
20 /* c_width*/
)
BU2834(
.D(BU2834_D),
.Q(BU2834_Q),
.CLK(BU2834_CLK),
.CE(BU2834_CE)
);
wire BU3029_CLK;
assign BU3029_CLK = n659;
wire [0 : 0] BU3029_D;
assign BU3029_D[0] = n579;
wire [0 : 0] BU3029_Q;
assign n7247 = BU3029_Q[0];
wire BU3029_CE;
assign BU3029_CE = n660;
C_SHIFT_RAM_V7_0 #(
1 /* c_addr_width*/,
"0" /* c_ainit_val*/,
"0" /* c_default_data*/,
2 /* c_default_data_radix*/,
2 /* c_depth*/,
0 /* c_enable_rlocs*/,
0 /* c_generate_mif*/,
0 /* c_has_a*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"null" /* c_mem_init_file*/,
2 /* c_mem_init_radix*/,
0 /* c_read_mif*/,
1 /* c_reg_last_bit*/,
0 /* c_shift_type*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU3029(
.CLK(BU3029_CLK),
.D(BU3029_D),
.Q(BU3029_Q),
.CE(BU3029_CE)
);
wire [0 : 0] BU3037_D;
assign BU3037_D[0] = n7190;
wire [0 : 0] BU3037_Q;
assign n7248 = BU3037_Q[0];
wire BU3037_CLK;
assign BU3037_CLK = n659;
wire BU3037_CE;
assign BU3037_CE = n660;
C_REG_FD_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU3037(
.D(BU3037_D),
.Q(BU3037_Q),
.CLK(BU3037_CLK),
.CE(BU3037_CE)
);
wire [0 : 0] BU3041_D;
assign BU3041_D[0] = n7189;
wire [0 : 0] BU3041_Q;
assign n7249 = BU3041_Q[0];
wire BU3041_CLK;
assign BU3041_CLK = n659;
wire BU3041_CE;
assign BU3041_CE = n660;
C_REG_FD_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU3041(
.D(BU3041_D),
.Q(BU3041_Q),
.CLK(BU3041_CLK),
.CE(BU3041_CE)
);
wire [19 : 0] BU2901_A;
assign BU2901_A[0] = n7171;
assign BU2901_A[1] = n7172;
assign BU2901_A[2] = n7173;
assign BU2901_A[3] = n7174;
assign BU2901_A[4] = n7175;
assign BU2901_A[5] = n7176;
assign BU2901_A[6] = n7177;
assign BU2901_A[7] = n7178;
assign BU2901_A[8] = n7179;
assign BU2901_A[9] = n7180;
assign BU2901_A[10] = n7181;
assign BU2901_A[11] = n7182;
assign BU2901_A[12] = n7183;
assign BU2901_A[13] = n7184;
assign BU2901_A[14] = n7185;
assign BU2901_A[15] = n7186;
assign BU2901_A[16] = n7187;
assign BU2901_A[17] = n7188;
assign BU2901_A[18] = n7189;
assign BU2901_A[19] = n7190;
wire [0 : 0] BU2901_B;
assign BU2901_B[0] = n7214;
wire [20 : 0] BU2901_Q;
assign n7193 = BU2901_Q[0];
assign n7194 = BU2901_Q[1];
assign n7195 = BU2901_Q[2];
assign n7196 = BU2901_Q[3];
assign n7197 = BU2901_Q[4];
assign n7198 = BU2901_Q[5];
assign n7199 = BU2901_Q[6];
assign n7200 = BU2901_Q[7];
assign n7201 = BU2901_Q[8];
assign n7202 = BU2901_Q[9];
assign n7203 = BU2901_Q[10];
assign n7204 = BU2901_Q[11];
assign n7205 = BU2901_Q[12];
assign n7206 = BU2901_Q[13];
assign n7207 = BU2901_Q[14];
assign n7208 = BU2901_Q[15];
assign n7209 = BU2901_Q[16];
assign n7210 = BU2901_Q[17];
assign n7211 = BU2901_Q[18];
assign n7212 = BU2901_Q[19];
wire BU2901_CLK;
assign BU2901_CLK = n659;
wire BU2901_CE;
assign BU2901_CE = n660;
C_ADDSUB_V7_0 #(
0 /* c_add_mode*/,
"000000000000000000000" /* c_ainit_val*/,
0 /* c_a_type*/,
20 /* c_a_width*/,
0 /* c_bypass_enable*/,
0 /* c_bypass_low*/,
0 /* c_b_constant*/,
1 /* c_b_type*/,
"000000000000000000000" /* c_b_value*/,
1 /* c_b_width*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_add*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
0 /* c_has_a_signed*/,
0 /* c_has_bypass*/,
0 /* c_has_bypass_with_cin*/,
0 /* c_has_b_in*/,
0 /* c_has_b_out*/,
0 /* c_has_b_signed*/,
1 /* c_has_ce*/,
0 /* c_has_c_in*/,
0 /* c_has_c_out*/,
0 /* c_has_ovfl*/,
1 /* c_has_q*/,
0 /* c_has_q_b_out*/,
0 /* c_has_q_c_out*/,
0 /* c_has_q_ovfl*/,
1 /* c_has_s*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
20 /* c_high_bit*/,
1 /* c_latency*/,
0 /* c_low_bit*/,
21 /* c_out_width*/,
0 /* c_pipe_stages*/,
"000000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/
)
BU2901(
.A(BU2901_A),
.B(BU2901_B),
.Q(BU2901_Q),
.CLK(BU2901_CLK),
.CE(BU2901_CE)
);
defparam BU3045.INIT = 'h7340;
wire BU3045_I0;
assign BU3045_I0 = n7248;
wire BU3045_I1;
assign BU3045_I1 = n7247;
wire BU3045_I2;
assign BU3045_I2 = n660;
wire BU3045_I3;
assign BU3045_I3 = n7251;
wire BU3045_O;
assign n7250 = BU3045_O;
LUT4 BU3045(
.I0(BU3045_I0),
.I1(BU3045_I1),
.I2(BU3045_I2),
.I3(BU3045_I3),
.O(BU3045_O)
);
defparam BU3047.INIT = 'h0200;
wire BU3047_I0;
assign BU3047_I0 = n7248;
wire BU3047_I1;
assign BU3047_I1 = n7249;
wire BU3047_I2;
assign BU3047_I2 = n7212;
wire BU3047_I3;
assign BU3047_I3 = n660;
wire BU3047_O;
assign n7251 = BU3047_O;
LUT4 BU3047(
.I0(BU3047_I0),
.I1(BU3047_I1),
.I2(BU3047_I2),
.I3(BU3047_I3),
.O(BU3047_O)
);
defparam BU3049.INIT = 'ha040;
wire BU3049_I0;
assign BU3049_I0 = n7248;
wire BU3049_I1;
assign BU3049_I1 = n7212;
wire BU3049_I2;
assign BU3049_I2 = n660;
wire BU3049_I3;
assign BU3049_I3 = n7247;
wire BU3049_O;
assign n7253 = BU3049_O;
LUT4 BU3049(
.I0(BU3049_I0),
.I1(BU3049_I1),
.I2(BU3049_I2),
.I3(BU3049_I3),
.O(BU3049_O)
);
wire [18 : 0] BU3051_D;
assign BU3051_D[0] = n7193;
assign BU3051_D[1] = n7194;
assign BU3051_D[2] = n7195;
assign BU3051_D[3] = n7196;
assign BU3051_D[4] = n7197;
assign BU3051_D[5] = n7198;
assign BU3051_D[6] = n7199;
assign BU3051_D[7] = n7200;
assign BU3051_D[8] = n7201;
assign BU3051_D[9] = n7202;
assign BU3051_D[10] = n7203;
assign BU3051_D[11] = n7204;
assign BU3051_D[12] = n7205;
assign BU3051_D[13] = n7206;
assign BU3051_D[14] = n7207;
assign BU3051_D[15] = n7208;
assign BU3051_D[16] = n7209;
assign BU3051_D[17] = n7210;
assign BU3051_D[18] = n7211;
wire [18 : 0] BU3051_Q;
assign n600 = BU3051_Q[0];
assign n601 = BU3051_Q[1];
assign n602 = BU3051_Q[2];
assign n603 = BU3051_Q[3];
assign n604 = BU3051_Q[4];
assign n605 = BU3051_Q[5];
assign n606 = BU3051_Q[6];
assign n607 = BU3051_Q[7];
assign n608 = BU3051_Q[8];
assign n609 = BU3051_Q[9];
assign n610 = BU3051_Q[10];
assign n611 = BU3051_Q[11];
assign n612 = BU3051_Q[12];
assign n613 = BU3051_Q[13];
assign n614 = BU3051_Q[14];
assign n615 = BU3051_Q[15];
assign n616 = BU3051_Q[16];
assign n617 = BU3051_Q[17];
assign n618 = BU3051_Q[18];
wire BU3051_CLK;
assign BU3051_CLK = n659;
wire BU3051_CE;
assign BU3051_CE = n660;
wire BU3051_SCLR;
assign BU3051_SCLR = n7250;
wire BU3051_SSET;
assign BU3051_SSET = n7253;
C_REG_FD_V7_0 #(
"0000000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
1 /* c_has_sclr*/,
0 /* c_has_sinit*/,
1 /* c_has_sset*/,
"0000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
19 /* c_width*/
)
BU3051(
.D(BU3051_D),
.Q(BU3051_Q),
.CLK(BU3051_CLK),
.CE(BU3051_CE),
.SCLR(BU3051_SCLR),
.SSET(BU3051_SSET)
);
wire [0 : 0] BU3132_D;
assign BU3132_D[0] = n7212;
wire [0 : 0] BU3132_Q;
assign n619 = BU3132_Q[0];
wire BU3132_CLK;
assign BU3132_CLK = n659;
wire BU3132_CE;
assign BU3132_CE = n660;
wire BU3132_SCLR;
assign BU3132_SCLR = n7253;
wire BU3132_SSET;
assign BU3132_SSET = n7250;
C_REG_FD_V7_0 #(
"0" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
1 /* c_has_sclr*/,
0 /* c_has_sinit*/,
1 /* c_has_sset*/,
"0" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
1 /* c_width*/
)
BU3132(
.D(BU3132_D),
.Q(BU3132_Q),
.CLK(BU3132_CLK),
.CE(BU3132_CE),
.SCLR(BU3132_SCLR),
.SSET(BU3132_SSET)
);
wire [19 : 0] BU2573_D;
assign BU2573_D[0] = n580;
assign BU2573_D[1] = n581;
assign BU2573_D[2] = n582;
assign BU2573_D[3] = n583;
assign BU2573_D[4] = n584;
assign BU2573_D[5] = n585;
assign BU2573_D[6] = n586;
assign BU2573_D[7] = n587;
assign BU2573_D[8] = n588;
assign BU2573_D[9] = n589;
assign BU2573_D[10] = n590;
assign BU2573_D[11] = n591;
assign BU2573_D[12] = n592;
assign BU2573_D[13] = n593;
assign BU2573_D[14] = n594;
assign BU2573_D[15] = n595;
assign BU2573_D[16] = n596;
assign BU2573_D[17] = n597;
assign BU2573_D[18] = n598;
assign BU2573_D[19] = n599;
wire [19 : 0] BU2573_Q;
assign n662 = BU2573_Q[0];
assign n663 = BU2573_Q[1];
assign n664 = BU2573_Q[2];
assign n665 = BU2573_Q[3];
assign n666 = BU2573_Q[4];
assign n667 = BU2573_Q[5];
assign n668 = BU2573_Q[6];
assign n669 = BU2573_Q[7];
assign n670 = BU2573_Q[8];
assign n671 = BU2573_Q[9];
assign n672 = BU2573_Q[10];
assign n673 = BU2573_Q[11];
assign n674 = BU2573_Q[12];
assign n675 = BU2573_Q[13];
assign n676 = BU2573_Q[14];
assign n677 = BU2573_Q[15];
assign n678 = BU2573_Q[16];
assign n679 = BU2573_Q[17];
assign n680 = BU2573_Q[18];
assign n681 = BU2573_Q[19];
wire BU2573_CLK;
assign BU2573_CLK = n659;
wire BU2573_CE;
assign BU2573_CE = n331;
C_REG_FD_V7_0 #(
"00000000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"00000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
20 /* c_width*/
)
BU2573(
.D(BU2573_D),
.Q(BU2573_Q),
.CLK(BU2573_CLK),
.CE(BU2573_CE)
);
wire [19 : 0] BU3141_D;
assign BU3141_D[0] = n600;
assign BU3141_D[1] = n601;
assign BU3141_D[2] = n602;
assign BU3141_D[3] = n603;
assign BU3141_D[4] = n604;
assign BU3141_D[5] = n605;
assign BU3141_D[6] = n606;
assign BU3141_D[7] = n607;
assign BU3141_D[8] = n608;
assign BU3141_D[9] = n609;
assign BU3141_D[10] = n610;
assign BU3141_D[11] = n611;
assign BU3141_D[12] = n612;
assign BU3141_D[13] = n613;
assign BU3141_D[14] = n614;
assign BU3141_D[15] = n615;
assign BU3141_D[16] = n616;
assign BU3141_D[17] = n617;
assign BU3141_D[18] = n618;
assign BU3141_D[19] = n619;
wire [19 : 0] BU3141_Q;
assign n682 = BU3141_Q[0];
assign n683 = BU3141_Q[1];
assign n684 = BU3141_Q[2];
assign n685 = BU3141_Q[3];
assign n686 = BU3141_Q[4];
assign n687 = BU3141_Q[5];
assign n688 = BU3141_Q[6];
assign n689 = BU3141_Q[7];
assign n690 = BU3141_Q[8];
assign n691 = BU3141_Q[9];
assign n692 = BU3141_Q[10];
assign n693 = BU3141_Q[11];
assign n694 = BU3141_Q[12];
assign n695 = BU3141_Q[13];
assign n696 = BU3141_Q[14];
assign n697 = BU3141_Q[15];
assign n698 = BU3141_Q[16];
assign n699 = BU3141_Q[17];
assign n700 = BU3141_Q[18];
assign n701 = BU3141_Q[19];
wire BU3141_CLK;
assign BU3141_CLK = n659;
wire BU3141_CE;
assign BU3141_CE = n331;
C_REG_FD_V7_0 #(
"00000000000000000000" /* c_ainit_val*/,
0 /* c_enable_rlocs*/,
0 /* c_has_aclr*/,
0 /* c_has_ainit*/,
0 /* c_has_aset*/,
1 /* c_has_ce*/,
0 /* c_has_sclr*/,
0 /* c_has_sinit*/,
0 /* c_has_sset*/,
"00000000000000000000" /* c_sinit_val*/,
0 /* c_sync_enable*/,
0 /* c_sync_priority*/,
20 /* c_width*/
)
BU3141(
.D(BU3141_D),
.Q(BU3141_Q),
.CLK(BU3141_CLK),
.CE(BU3141_CE)
);
//synopsys translate_on
endmodule