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Signals index

A
 a : beta2 : wire
Connects down to:shift_right:sr:a 
 a : shift_right : input
Connects up to:beta2:sr:a 
 ac97_bit_clock : labkit_beta2demo : input
 ac97_sdata_in : labkit_beta2demo : input
 ac97_sdata_out : labkit_beta2demo : output
 ac97_synch : labkit_beta2demo : output
 addr : lab9 : input
Connects down to:RAMB16_S9:m0:ADDR , RAMB16_S9:m1:ADDR , RAMB16_S9:m2:ADDR , RAMB16_S9:m3:ADDR 
Connects up to:labkit_beta2demo:mem:ma 
 addr : xfont : input
Connects down to:RAMB16_S9:font:ADDR 
Connects up to:vga:f:font_addr 
 addra : xcmem : input
Connects down to:RAMB16_S4_S18:mlo:ADDRA , RAMB16_S4_S18:mhi:ADDRA 
Connects up to:vga:b:char_addr 
 addrb : xcmem : input
Connects down to:RAMB16_S4_S18:mlo:ADDRB , RAMB16_S4_S18:mhi:ADDRB 
Connects up to:vga:b:maddr 
 addsub : beta2 : wire
 addsub_n : beta2 : wire
 addsub_op : beta2 : wire
Connects down to:decode:ctl:addsub_op 
 addsub_op : decode : output reg
Connects up to:beta2:ctl:addsub_op 
 addsub_v : beta2 : wire
 addsub_z : beta2 : wire
 analyzer1_clock : labkit_beta2demo : output
 analyzer1_data : labkit_beta2demo : output
 analyzer2_clock : labkit_beta2demo : output
 analyzer2_data : labkit_beta2demo : output
 analyzer3_clock : labkit_beta2demo : output
 analyzer3_data : labkit_beta2demo : output
 analyzer4_clock : labkit_beta2demo : output
 analyzer4_data : labkit_beta2demo : output
 annul : decode : reg
 anodes : segdisplay : output reg
 anodes : simulate : wire
Connects down to:beta2demo:uut:anodes 
 asel : beta2 : wire
Connects down to:decode:ctl:asel 
 asel : decode : output reg
Connects up to:beta2:ctl:asel 
 audio_reset_b : labkit_beta2demo : output
B
 b : beta2 : wire
Connects down to:shift_right:sr:b 
 b : shift_right : input
Connects up to:beta2:sr:b 
 beep : labkit_beta2demo : output
 blank : labkit_beta2demo : wire
Connects down to:vga:dpy:blank 
 blank : vga : output wire
Connects up to:labkit_beta2demo:dpy:blank 
 boole : beta2 : wire
 boole_and : beta2 : wire
Connects down to:decode:ctl:boole_and 
 boole_and : decode : output reg
Connects up to:beta2:ctl:boole_and 
 boole_or : beta2 : wire
Connects down to:decode:ctl:boole_or 
 boole_or : decode : output reg
Connects up to:beta2:ctl:boole_or 
 borderpix : vga : wire
 branch : beta2 : wire
Connects down to:decode:ctl:branch 
 branch : decode : output reg
Connects up to:beta2:ctl:branch 
 bsel : beta2 : wire
Connects down to:decode:ctl:bsel 
 bsel : decode : output reg
Connects up to:beta2:ctl:bsel 
 button0 : labkit_beta2demo : input
 button1 : labkit_beta2demo : input
 button2 : labkit_beta2demo : input
 button3 : labkit_beta2demo : input
 button_down : labkit_beta2demo : input
 button_enter : labkit_beta2demo : input
Connects down to:debounce:dbreset:noisy 
 button_left : labkit_beta2demo : input
 button_right : labkit_beta2demo : input
 button_up : labkit_beta2demo : input
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