Prev PageHierarchyFilesModulesSignalsTasksFunctionsHelp
ABCDEFHIKLMNOPRSTUVWXYZ

Signals index

C
 c : beta2 : wire
 char : vga : wire
Connects down to:xcmem:b:douta 
 char_addr : vga : wire
Connects down to:xcmem:b:addra 
 char_index : display_16hex : reg
 clean : debounce : output reg
Connects up to:labkit_beta2demo:dbreset:user_reset 
 clk : beta2 : input (used in @posedge)
Connects down to:decode:ctl:clk 
Connects up to:labkit_beta2demo:cpu:clk 
 clk : clock300hz : input (used in @posedge)
Connects up to:labkit_beta2demo:c1:clk 
 clk : decode : input (used in @posedge)
Connects up to:beta2:ctl:clk 
 clk : lab9 : input
Connects down to:RAMB16_S9:m0:CLK , RAMB16_S9:m1:CLK , RAMB16_S9:m2:CLK , RAMB16_S9:m3:CLK 
Connects up to:labkit_beta2demo:mem:clk 
 clk : labkit_beta2demo : wire (used in @posedge)
Connects down to:SRL16:reset_sr:CLK , debounce:dbreset:clock , clock300hz:c1:clk , beta2:cpu:clk , lab9:mem:clk , vga:dpy:clk , ps2:kbd:clk , display_16hex:hexdisp1:clock_27mhz 
 clk : ps2 : input (used in @posedge)
Connects up to:labkit_beta2demo:kbd:clk 
 clk : segdisplay : input (used in @posedge)
 clk : simulate : reg
Connects down to:beta2demo:uut:clk 
 clk : vga : input (used in @posedge)
Connects down to:xcmem:b:clka , xcmem:b:clkb , xfont:f:clk 
Connects up to:labkit_beta2demo:dpy:clk 
 clk : xfont : input
Connects down to:RAMB16_S9:font:CLK 
Connects up to:vga:f:clk 
 clka : xcmem : input
Connects down to:RAMB16_S4_S18:mlo:CLKA , RAMB16_S4_S18:mhi:CLKA 
Connects up to:vga:b:clk 
 clkb : xcmem : input
Connects down to:RAMB16_S4_S18:mlo:CLKB , RAMB16_S4_S18:mhi:CLKB 
Connects up to:vga:b:clk 
 clk_300Hz : clock300hz : output wire
Connects up to:labkit_beta2demo:c1:clk_300Hz 
 clk_300Hz : labkit_beta2demo : wire
Connects down to:clock300hz:c1:clk_300Hz , ps2:kbd:watchdog 
 clock : debounce : input (used in @posedge)
Connects up to:labkit_beta2demo:dbreset:clk 
 clock : display_16hex : reg (used in @posedge)
 clock1 : labkit_beta2demo : input
 clock2 : labkit_beta2demo : input
 clock_27mhz : display_16hex : input (used in @posedge)
Connects up to:labkit_beta2demo:hexdisp1:clk 
 clock_27mhz : labkit_beta2demo : input
Connects down to:DCM:vclk1:CLKIN 
 clock_50MHz : labkit_beta2demo : wire
Connects down to:BUFG:vclk2:O 
 clock_50mhz_unbuf : labkit_beta2demo : wire
Connects down to:DCM:vclk1:CLKFX , BUFG:vclk2:I 
 clock_feedback_in : labkit_beta2demo : input
 clock_feedback_out : labkit_beta2demo : output
 cmp : beta2 : wire
 cmp_eq : beta2 : wire
Connects down to:decode:ctl:cmp_eq 
 cmp_eq : decode : output reg
Connects up to:beta2:ctl:cmp_eq 
 cmp_lt : beta2 : wire
Connects down to:decode:ctl:cmp_lt 
 cmp_lt : decode : output reg
Connects up to:beta2:ctl:cmp_lt 
 column : vga : reg
 control : display_16hex : reg
 count : debounce : reg
 count : display_16hex : reg
 count : ps2 : reg
 csel : beta2 : wire
Connects down to:decode:ctl:csel 
 csel : decode : output reg
Connects up to:beta2:ctl:csel 
D
 data : display_16hex : input
Connects up to:labkit_beta2demo:hexdisp1:dispdata 
 daughtercard : labkit_beta2demo : inout
 digit : segdisplay : reg
 din : lab9 : input
Connects down to:RAMB16_S9:m0:DI , RAMB16_S9:m1:DI , RAMB16_S9:m2:DI , RAMB16_S9:m3:DI 
Connects up to:labkit_beta2demo:mem:mdout 
 dinb : xcmem : input
Connects down to:RAMB16_S4_S18:mlo:DIB , RAMB16_S4_S18:mlo:DIB , RAMB16_S4_S18:mlo:DIB , RAMB16_S4_S18:mlo:DIB , RAMB16_S4_S18:mhi:DIB , RAMB16_S4_S18:mhi:DIB , RAMB16_S4_S18:mhi:DIB , RAMB16_S4_S18:mhi:DIB 
Connects up to:vga:b:mdin 
 dispdata : labkit_beta2demo : wire
Connects down to:display_16hex:hexdisp1:data 
 display : segdisplay : reg
 disp_blank : display_16hex : output
Connects up to:labkit_beta2demo:hexdisp1:disp_blank 
 disp_blank : labkit_beta2demo : output
Connects down to:display_16hex:hexdisp1:disp_blank 
 disp_ce_b : display_16hex : output reg
Connects up to:labkit_beta2demo:hexdisp1:disp_ce_b 
 disp_ce_b : labkit_beta2demo : output
Connects down to:display_16hex:hexdisp1:disp_ce_b 
 disp_clock : display_16hex : output
Connects up to:labkit_beta2demo:hexdisp1:disp_clock 
 disp_clock : labkit_beta2demo : output
Connects down to:display_16hex:hexdisp1:disp_clock 
 disp_data_in : labkit_beta2demo : input
 disp_data_out : display_16hex : output reg
Connects up to:labkit_beta2demo:hexdisp1:disp_data_out 
 disp_data_out : labkit_beta2demo : output
Connects down to:display_16hex:hexdisp1:disp_data_out 
 disp_reset_b : display_16hex : output reg
Connects up to:labkit_beta2demo:hexdisp1:disp_reset_b 
 disp_reset_b : labkit_beta2demo : output
Connects down to:display_16hex:hexdisp1:disp_reset_b 
 disp_rs : display_16hex : output reg
Connects up to:labkit_beta2demo:hexdisp1:disp_rs 
 disp_rs : labkit_beta2demo : output
Connects down to:display_16hex:hexdisp1:disp_rs 
 dots : display_16hex : reg
 dot_index : display_16hex : reg
 dout : lab9 : output
Connects down to:RAMB16_S9:m0:DO , RAMB16_S9:m1:DO , RAMB16_S9:m2:DO , RAMB16_S9:m3:DO 
Connects up to:labkit_beta2demo:mem:ramout 
 douta : xcmem : output
Connects down to:RAMB16_S4_S18:mlo:DOA , RAMB16_S4_S18:mhi:DOA 
Connects up to:vga:b:char 
 doutb : xcmem : output
Connects down to:RAMB16_S4_S18:mlo:DOB , RAMB16_S4_S18:mlo:DOB , RAMB16_S4_S18:mlo:DOB , RAMB16_S4_S18:mlo:DOB , RAMB16_S4_S18:mhi:DOB , RAMB16_S4_S18:mhi:DOB , RAMB16_S4_S18:mhi:DOB , RAMB16_S4_S18:mhi:DOB 
Connects up to:vga:b:mdout 
 dpyout : labkit_beta2demo : wire
Connects down to:vga:dpy:mdout 
 dreset : display_16hex : wire
ABCDEFHIKLMNOPRSTUVWXYZ
Next PageHierarchyFilesModulesSignalsTasksFunctionsHelp
This page: Created:Thu Dec 8 21:44:34 2005
Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).Help