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Signals index

U
 user1 : labkit_beta2demo : inout
 user2 : labkit_beta2demo : inout
 user3 : labkit_beta2demo : inout
 user4 : labkit_beta2demo : inout
 user_reset : labkit_beta2demo : wire
Connects down to:debounce:dbreset:clean 
V
 v : vga : reg
 value : segdisplay : input
 vblank : vga : reg
 vblankon : vga : wire
 vcount : vga : reg
 vga_out_blank_b : labkit_beta2demo : output
 vga_out_blue : labkit_beta2demo : output
 vga_out_green : labkit_beta2demo : output
 vga_out_hsync : labkit_beta2demo : output
Connects down to:vga:dpy:hsync 
 vga_out_pixel_clock : labkit_beta2demo : output
 vga_out_red : labkit_beta2demo : output
 vga_out_sync_b : labkit_beta2demo : output
 vga_out_vsync : labkit_beta2demo : output
Connects down to:vga:dpy:vsync 
 vreset : vga : wire
 vsync : simulate : wire
Connects down to:beta2demo:uut:vsync 
 vsync : vga : output reg
Connects up to:labkit_beta2demo:dpy:vga_out_vsync 
 vsyncoff : vga : wire
 vsyncon : vga : wire
W
 w : shift_right : wire
 wa : beta2 : wire
 wasel : beta2 : wire
Connects down to:decode:ctl:wasel 
 wasel : decode : output reg
Connects up to:beta2:ctl:wasel 
 watchdog : ps2 : input
Connects up to:labkit_beta2demo:kbd:clk_300Hz 
 wd : beta2 : wire
 wd_addsub : beta2 : wire
Connects down to:decode:ctl:wd_addsub 
 wd_addsub : decode : output reg
Connects up to:beta2:ctl:wd_addsub 
 wd_boole : beta2 : wire
Connects down to:decode:ctl:wd_boole 
 wd_boole : decode : output reg
Connects up to:beta2:ctl:wd_boole 
 wd_cmp : beta2 : wire
Connects down to:decode:ctl:wd_cmp 
 wd_cmp : decode : output reg
Connects up to:beta2:ctl:wd_cmp 
 wd_mult : beta2 : wire
Connects down to:decode:ctl:wd_mult 
 wd_mult : decode : output reg
Connects up to:beta2:ctl:wd_mult 
 wd_shift : beta2 : wire
Connects down to:decode:ctl:wd_shift 
 wd_shift : decode : output reg
Connects up to:beta2:ctl:wd_shift 
 we : lab9 : input
Connects down to:RAMB16_S9:m0:WE , RAMB16_S9:m1:WE , RAMB16_S9:m2:WE , RAMB16_S9:m3:WE 
Connects up to:labkit_beta2demo:mem:mwe , labkit_beta2demo:mem:sel_ram 
 web : xcmem : input
Connects down to:RAMB16_S4_S18:mlo:WEB , RAMB16_S4_S18:mhi:WEB 
Connects up to:vga:b:mwe 
 werf : beta2 : wire
Connects down to:decode:ctl:werf 
 werf : decode : output
Connects up to:beta2:ctl:werf 
 wptr : ps2 : reg
 wptr_inc : ps2 : wire
X
 x : shift_right : wire
 xadr : beta2 : input
Connects up to:labkit_beta2demo:cpu:irq_addr 
 xb : beta2 : wire
Y
 y : shift_right : wire
Z
 z : beta2 : wire
Connects down to:decode:ctl:z 
 z : decode : input
Connects up to:beta2:ctl:z 
 z : shift_right : wire
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This page: Created:Thu Dec 8 21:44:34 2005
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