| Lectures |
- L01: Multicore Intro [PDF]
- L01: Beehive Overview [PDF]
- L02: Computation Models [PDF]
- L02 & L03: Intro to Verilog [PDF, NewMessenger.v]
- L04: Parallel Computing Patterns [PDF]
- L05: Parallel TSP [PDF]
- L06: Hardware Transactional Memory on Beehive [PDF]
- L07: Shared Memory Architectures Programming and Synchronization [PDF]
- L08: Shared Memory Programming and Wait-Free Synchronization [PDF]
- L09: Shared Memory Software Coherence and Fences [PDF]
- L10: Shared Memory Cache Coherence [PDF]
- L11: Shared Memory Cache Coherence II [PDF]
- L12: Final Projects, Quiz1 Review, Labs 3 and 4 [PDF]
- L13: Shared Memory Cache Coherence III [PDF]
- L14: Interconnection Networks [PDF]
- L15: Scalable Synchronization [PDF]
- L16: Interconnection Networks II [PDF]
- L17: Interconnection Networks III [PDF]
- L18: Case Study I: Tilera Multicore [PDF]
- L19: Case Study II: AMD CC and Linux Scalability [PDF]
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| Labs | |
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Beehive
Docs |
- Beehive: A many-core computer for FGPAs [PDF]
- Apiary: Software Tools for Beehive [PDF]
- libmc: a Multi-core Library for Beehive [PDF]
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Other
Docs |
- Xilinx XUPV5 Board User Guide [PDF]
- Verilog Reference Guide [PDF]
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