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Appendix: Tips and Tricks

AC97 Codec Tips

  • Cold resets reset all registers and should be used to restore the codec to its initial state. Warm resets are used for power saving modes. Unless you are running in low power modes, you can ignore the use of warm resets.
  • When the codec comes out of reset (reset transition from low to high), the signals sdata_out and sync MUST be held low. Failure to do so will cause unexpected codec behavior that may be a vendor test mode. These test modes are not documented well in the LM4550 specification.
  • Look at sdata_out and sdata_in on the logic analyzer often. Finding early problems in reading and writing will help speed up the debugging process.
  • At 12.288 MHz, 1 bit is approx. 81 ns on the logic analyzer.

Xilinx Tips and Hints

  • Copy your project on the local drive of the machine you are on instead of the shared drive. Xilinx will compile much faster. Don’t forget to place a copy back in your shared folder once you finish because there is no guarantee you will get the same computer!! A FATAL GuiUtility error usually means the project file is corrupt. Start a new Xilinx project and copy your .v files over to the new project.
  • Don’t forget the .UCF constraints file!
  • Xilinx core 1024 pt Complex FFT module would compile in project, but would cause “Invalid SDR Directive” error during ACE file generation. No fix found.
  • Xilinx does not check typos on variable names. Will create misnamed wires, registers etc.
  • Always make sure you are building the correct file (labkit.v). Compiling and generating the ACE file for the wrong .v file will cause a kit error.
  • The Xilinx ISE environment seems to have many transient errors. Most can be solved simply by restarting Xilinx ISE.