The Fifth Young Architect Workshop

Welcome to the Young Architect Workshop!

A Workshop for Early-stage Graduate Students in Computer Architecture

The Young Architect Workshop (YArch, pronounced “why arch”) is a workshop for junior graduate students and research-active undergraduate students studying computer architecture and related fields. This year's YArch is organized in conjunction with the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2023).

The central theme of the YArch workshop is to serve as a welcoming venue for early-stage graduate students (or undergrads interested in research) to present their ongoing work and receive feedback from experts within the community. In addition, this workshop aims to help students in building connections both with their peers and established architects in the community. To this end, YArch will include:

  • Route to Top-tier: Each submitted work will receive two or more expert reviews. The aim of these reviews will be to give early guidance on important boxes to check for the submitted work to be a future successful top tier conference paper.
  • Meet an Architect: As part of the workshop, attendees will be paired with experts in their chosen research area to get feedback on their ongoing work and future research directions.
  • Becoming an Architect: The workshop will include keynote talks from academic and industry leaders specifically geared towards early stage graduate students.
  • Ask an Architect: The workshop will include a panel of established architects in industry and academia from whom students can seek career advice.


Paper registration deadline: January 20th, 2023
Paper submission deadline: January 27th, 2023
Notification of acceptance: February 22nd, 2023
Workshop date (with ASPLOS): March 26th, 2023 (Sunday)





Dimitrios Skarlatos, CMU
Suvinay Subramanian, Google
Mengjia Yan, MIT
John Alsop, AMD


Time (local) Event
9:00-9:15am Welcome
9:15-10:15am Keynote 1: The Whole is Greater than the Sum of Its Parts: a Story of Cross-stack Collaborations
Speaker: Tushar Krishna
10:20-10:40am Coffee Break
10:40-12:00pm Panel Discussion: Demystifying Grad School
Panelist: Trevor E. Carlson (moderator), Bilge Acun, Poulami Das, Lieven Eeckhout, Prashant Nair
12:00-01:40pm Lunch + Round-table Mentoring
1:40-2:40pm Keynote 2: Practical Advice for a Successful and Happy Career in Research
Speaker: Martin Maas
2:40-3:20pm Lightning Talks
3:20-3:40pm Coffee Break
3:40-4:40pm Poster Session
4:45-5:00pm Closing Remarks

Keynote 1: The Whole is Greater than the Sum of Its Parts: a Story of Cross-stack Collaborations

Speaker: Tushar Krishna (Georgia Tech)


Abstract: A PhD teaches us to go deep - super-specializing in one topic area. Through the problems we solve and the papers we write, we gain a deep understanding of a very niche topic - more of than not becoming the only person in the world who understands and appreciates it. Unfortunately, this also puts us into a bubble, missing the forest for the trees. In this talk, I will walk through my experiences through grad school and faculty life in getting out of my own research bubble, gaining an understanding for bigger problems, and solving them with the help of smart collaborators.

Bio: Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech. He also serves as an Associate Director for the Center for Research into Novel Computing Hierarchies (CRNCH). He held the ON Semiconductor (Endowed) Junior Professorship from 2019-2021. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007). Before joining Georgia Tech in 2015, Dr. Krishna spent a year as a researcher at the VSSAD group at Intel, Massachusetts.
Dr. Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems. His research is funded via multiple awards from NSF, DARPA, IARPA, Department of Energy, Intel, Google, Facebook, Qualcomm and TSMC. His papers have been cited over 11,000 times. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and four have won best paper awards. He was inducted into the HPCA Hall of Fame in 2022. He received the “Class of 1940 Course Survey Teaching Effectiveness” Award from Georgia Tech in 2018 and the “Roger P. Webb Outstanding Junior Faculty Award” from the School of ECE in Georgia Tech in 2021.

Keynote 2: Practical Advice for a Successful and Happy Career in Research

Speaker: Martin Maas (Google Research)


Abstract: As scientists, we strive to take an intentional and mindful approach to research, whether we are running an experiment or writing a research paper. However, a similarly intentional and mindful approach is required when it comes to our career choices and selecting the problems we work on. In this talk, I will reflect on common trade-offs associated with these decisions and distill them into practical advice on balancing different objectives of a research career.

Bio: Martin Maas is a Staff Research Scientist at Google Research, where he is part of the Google Brain team. His research interests are in language runtimes, computer architecture, systems, and machine learning, with a focus on applying machine learning to systems problems. He also chairs the J Extension group within the RISC-V project, which investigates hardware extensions for managed runtimes. Martin holds a BA in Computer Science from the University of Cambridge, as well as MS and PhD degrees in Computer Science from the University of California at Berkeley, where he worked on hardware support for managed languages and architectural support for memory-trace obliviousness.

Panel Discussion: Demystifying Grad School

Moderator: Trevor E. Carlson (National University of Singapore)


Trevor E. Carlson is an Assistant Professor at the School of Computing at the National University of Singapore, and previously worked as a computer architect at IBM and as a postdoctoral researcher at Uppsala University. He studied at Carnegie Mellon University (BS, MS) and Ghent University (PhD). His interests include secure and efficient computing and accelerator design, as well as simulation and sampling methodologies. He co-develops the Sniper Multi-Core Simulator, which is being used by hundreds of researchers in academia and industry to evaluate the performance and power-efficiency of next generation systems. He has recently been awarded Amazon, Intel and VMWare Research Awards. His work has received six Best Paper or Best Paper Nominations in conferences such as the International Symposium on Microarchitecture (MICRO) and the International Symposium on Performance Analysis of Systems and Software (ISPASS).

Panelist: Bilge Acun (Meta)


Bilge Acun is a Research Scientist at Meta AI/FAIR, SysML team. She is working on making large scale machine learning systems more efficient and sustainable through algorithmic and system optimizations. She received her Ph.D. degree in 2017 at the Department of Computer Science at Universtiy of Illinois at Urbana-Champaign. Before joining Meta, she worked at the IBM Thomas J. Watson Research Center as a Research Staff Member.

Panelist: Poulami Das (Georgia Tech)


Poulami is a PhD candidate advised by Prof. Moin Qureshi at Georgia Tech. Her research focuses on software and architecture for improving the reliability of quantum computers and frequently appears at ASPLOS, MICRO, HPCA, and ISCA. She is also interested in computer architecture, memory systems, and emerging technologies.

Panelist: Lieven Eeckhout (Ghent University)


Lieven Eeckhout (PhD 2002) is a Full Professor at Ghent University, Belgium. His research interests include computer architecture, with specific emphasis on performance evaluation and modeling, dynamic resource management, CPU/GPU microarchitecture, and sustainability. He is the recipient of the 2017 ACM SIGARCH Maurice Wilkes Award and the 2017 OOPSLA Most Influential Paper Award, and he was elevated to IEEE Fellow in 2018 and ACM Fellow in 2021. He served as the Program Chair for ISCA 2020, HPCA 2015, CGO 2013 and ISPASS 2009. He has served as technical program committee member for 50+ computer architecture conferences, and he has graduated 23 PhD students.

Panelist: Prashant Nair (University of British Columbia)


Prashant Nair is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of British Columbia. He received his Ph.D. and M.Sc. in Electrical and Computer Engineering from the Georgia Institute of Technology and his B.Eng degree in Electronics Engineering from the University of Mumbai. Prashant was a Postdoctoral Researcher (Research Scientist) at IBM Thomas J. Watson Research Center in New York.
Prashant’s interests are in the areas of reliability, security, and performance-power efficient memory systems. He is also interested in system-level and architecture-level optimization to enable efficient and practical quantum computers. He frequently publishes in several top-tier conferences like ISCA, MICRO, HPCA, and ASPLOS. Prashant has served as a primary reviewer for several major conferences in computer architecture, including ISCA, ASPLOS-2016, IEEE CAL, ACM-TACO, ACM-TC, and SBAC-PAD.




Applicants must be either (a) research-active undergraduate students aiming for graduate school, or (b) graduate students (Masters and/or PhD) in computer architecture and related fields who have completed less than 3 years of graduate school at the time of the workshop. A note from the student’s research advisor attesting this is required as part of the submission.

Eligible students are invited to submit their early stage or on-going work to this workshop. Submitted work should not have been presented as part of a prior ACM/IEEE conference.

Note: This workshop is not a venue for publication and there will be no formal proceedings.

Topics of Interest

The workshop invites papers from all areas of computer architecture, broadly defined. Topics of interest include, but not limited to:

Submission Guidelines

The goal of this workshop is to help students think about a problem/idea in an holistic manner and communicate your ideas to the wider community, so that we can provide some valuable early-stage feedback. To this end, we encourage you to cover the following aspects in your submission:

Submission Details

Declaring Conflicts

When registering a submission, all its co-authors must provide information about conflicts with the YArch’23 program committee members. You are conflicted with a member if:

  1. you are currently employed at the same institution, have been previously employed at the same institution within the past two years (2020 or later), or are going to begin employment at the same institution;
  2. you have a past or present association as thesis advisor or advisee (no time limit);
  3. you have collaborated on a project, publication, grant proposal, or editorship within the past two years (2020 or later);
  4. or, you have spouse or first-degree relative relations.


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