PROGRAM

Time (local)	Event
9:00-9:15am	Welcome
9:15-10:15am	Keynote 1
10:20-10:40am	Coffee Break
10:40-12:00pm	Panel Discussion
12:00-01:40pm	Lunch + Round-table Mentoring
1:40-2:40pm	Keynote 2
2:40-3:20pm	Lightning Talks
3:20-3:40pm	Coffee Break
3:40-4:40pm	Poster Session
4:45-5:00pm	Closing Remarks

ACCEPTED PAPERS:

• Hardware for Event-driven Architectures
  David Schall (University of Edinburgh)
• HammerSim: A Tool to Model Rowhammer
  Kaustav Goswami; Ayaz Akram; Hari Venugopalan; Jason Lowe-Power (University of California, Davis)
• Analyzing Secure Non-Volatile Memory
  Chia Jen Cheng (Boston University); Samuel Thomas (Brown University); Tali Moreshet (Boston University); Maurice Herlihy (Brown University); Iris Bahar (Colorado School of Mines)
• Formal Pre-silicon Verification of Processors and Hardware Accelerators
  Saranyu Chattopadhyay; Caroline Trippel; Clark Barrett; Subhasish Mitra (Stanford University)
• LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators
  Michael Gilbert; Nellie Wu (MIT); Angshuman Parashar (NVIDIA); Joel Emer (MIT/NVIDIA); Vivienne Sze (MIT)
• Probabilistic Memory Consistency Specifications
  Reese Levine (UC Santa Cruz)
• Dataflow Blocks: Modular Time-Multiplexing for CGRAs
  Xuesi Chen; Nishanth Subramanian; Karthik Ramanathan; Nathan Beckmann; Brandon Lucia (Carnegie Mellon University)
• Leveraging Causality for Server Resource Provisioning
  Varun Gohil (Massachusetts Institute of Technology); Sundar Dev; David Lo; Parthasarathy Ranganathan (Google); Christina Delimitrou (Massachusetts Institute of Technology)
• Optimizing Temporal Motif Mining On A GPU
  Yichao Yuan; Haojie Ye (University of Michigan); Sanketh Vedula (Technion); Nishil Talati (University of Michigan/AMD Research)
• Formal Characterization of Hardware Transmitters for Secure Software and Hardware Repair
  Yao Hsiao (Stanford University); Christopher Fletcher (University of Illinois at Urbana-Champaign); Caroline Trippel (Stanford University)
• A Case for Aggressive Speculative Execution for VQA Optimization
  Suhas K Vittal (Georgia Tech)
• Hardware Support for Efficient and Secure Resource Harvesting in the Cloud
  Jovan Stojkovic (UIUC); Chunao Liu; Muhammad Shahbaz (Purdue University); Josep Torrellas (UIUC)
• Exploiting Data Commonality in Value Prediction
  Haiyue Ma; David Wentzlaff (Princeton University)
• A Neuromorphic Architecture for Online Learning in Brain-Computer Interfaces
  Michał Gerasimiuk; Andrew Milas; Karthik Sriram (Yale University); Brieuc Balon (Université catholique de Louvain); Ryan Jin (Yale University); James E. Smith (University of Wisconsin (Emeritus)); Abhishek Bhattacharjee (Yale University)
• Dynamic Speculation Control of Modern Processors
  Sankara Prasad Ramesh; Dean Tullsen (University of California San Diego)
• Minimal System-Level Test Synthesis from RTL for Hyperscale SDC Detection
  Brandon D'Agostino; Subhasish Mitra; Caroline Trippel (Stanford University)
• Near-Memory Acceleration of Far Memory
  Neel Patel; Mohammad Alian (University of Kansas)
• Accelerating Sparse Tensor Algebra by Overbooking Buffer Occupancy
  Fisher Xue; Nellie Wu (MIT); Joel Emer (MIT/NVIDIA); Vivienne Sze (MIT)
• SplitSim: Scalable and Parallel Full Data Center System Simulations
  Hejing Li; Antoine Kaufmann (Max Planck Institute for Software Systems)
• Detecting Microarchitectural Vulnerabilities via Fuzz Testing of White-box CPUs
  Bo Fu; Alaa Alameldeen (Simon Fraser University); Gururaj Saileshwar (University of Toronto/NVIDIA Research)
• CXLMemSim: A pure software simulated CXL.mem for performance characterization
  Yiwei Yang; Pooneh Safayenikoo (University of California, Santa Cruz); Jiacheng Ma; Tanvir Ahmed Khan (University of Michigan); Andrew Quinn (University of California, Santa Cruz)
• ConstSpec: Mitigating Cache-based Spectre Attacks via Fine-Gain Constant-Time Accesses
  Arash Pashrashid; Trevor E. Carlson (National University of Singapore)
• SMAD: Efficiently Defending Against Transient Execution Attacks
  Ange Thierry Ishimwe; Tamara Lehman (University of Colorado Boulder)

SUBMIT

Eligibility

Applicants must be either (a) research-active undergraduate students aiming for graduate school, or (b) graduate students (Masters and/or PhD) in computer architecture and related fields who have completed less than 3 years of graduate school at the time of the workshop. A note from the student’s research advisor attesting this is required as part of the submission.

Eligible students are invited to submit their early stage or on-going work to this workshop. Submitted work should not have been presented as part of a prior ACM/IEEE conference.

Note: This workshop is not a venue for publication and there will be no formal proceedings.

Topics of Interest

The workshop invites papers from all areas of computer architecture, broadly defined. Topics of interest include, but not limited to:

• Datacenter systems
• Hardware acceleration
• Memory hierarchy
• Virtualization
• Security
• Microarchitecture
• GPUs
• Parallel architectures
• Emerging technologies

Submission Guidelines

The goal of this workshop is to help students think about a problem/idea in an holistic manner and communicate your ideas to the wider community, so that we can provide some valuable early-stage feedback. To this end, we encourage you to cover the following aspects in your submission:

• Scope of problem/idea: Provide clear context for and scope of the problem(s) or idea(s) you intend to work on. This will likely form the basis of the introduction/background sections of your future work(s).
• Solution: Provide an overview of the design and implementation aspects of your solution(s) to the problem(s) described above. Given this is on-going work, focus more on providing breadth than depth. For example, beside describing the design of your idea, enlist the various system aspects which your proposed solutions will affect (e.g. does your proposed solution affect coherence protocols?) and that if you plan to discuss these effects in your future submission(s).
• Evaluation methodology: Discuss the evaluation methodology you plan to adopt to test the efficacy of your ideas. For example, the workloads that you plan to use, the tools you’ll employ (e.g., architectural simulator, real world experiments, FPGA prototypes), etc.
• Related work: This can be the traditional related work section. Please specify if you plan to quantitatively compare against some prior work.

Submission Details

• Submissions must be PDF files, in 2-column, single-spaced, 10pt format, at most 2 pages long, not including references.
• Submissions are double-blind. Please do not have any author identifying information in the paper submitted.
• Please have your research advisor send the workshop organizers an email with the following subject line “<Your name> meets YArch’23 eligibility requirements” to youngarchitectw@gmail.com.
• Submission site: https://yarch2023.hotcrp.com
• Registration deadline: January 20th, 2023, 23:59pm EST
• Submission deadline: January 27th, 2023, 23:59pm EST

Declaring Conflicts

When registering a submission, all its co-authors must provide information about conflicts with the YArch’23 program committee members. You are conflicted with a member if:

1. you are currently employed at the same institution, have been previously employed at the same institution within the past two years (2020 or later), or are going to begin employment at the same institution;
2. you have a past or present association as thesis advisor or advisee (no time limit);
3. you have collaborated on a project, publication, grant proposal, or editorship within the past two years (2020 or later);
4. or, you have spouse or first-degree relative relations.

Sponsors: