PROGRAM

Time (local)	Event
9:00-9:15am	Welcome
9:15-10:15am	Keynote 1: The Whole is Greater than the Sum of Its Parts: a Story of Cross-stack Collaborations Speaker: Tushar Krishna
10:20-10:40am	Coffee Break
10:40-12:00pm	Panel Discussion: Demystifying Grad School Panelist: Trevor E. Carlson (moderator), Bilge Acun, Poulami Das, Lieven Eeckhout, Prashant Nair
12:00-01:40pm	Lunch + Round-table Mentoring
1:40-2:40pm	Keynote 2: Practical Advice for a Successful and Happy Career in Research Speaker: Martin Maas
2:40-3:20pm	Lightning Talks
3:20-3:40pm	Coffee Break
3:40-4:40pm	Poster Session
4:45-5:00pm	Closing Remarks

Keynote 1: The Whole is Greater than the Sum of Its Parts: a Story of Cross-stack Collaborations (Recording)

Speaker: Tushar Krishna (Georgia Tech)

Abstract: A PhD teaches us to go deep - super-specializing in one topic area. Through the problems we solve and the papers we write, we gain a deep understanding of a very niche topic - more of than not becoming the only person in the world who understands and appreciates it. Unfortunately, this also puts us into a bubble, missing the forest for the trees. In this talk, I will walk through my experiences through grad school and faculty life in getting out of my own research bubble, gaining an understanding for bigger problems, and solving them with the help of smart collaborators.

Bio: Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech. He also serves as an Associate Director for the Center for Research into Novel Computing Hierarchies (CRNCH). He held the ON Semiconductor (Endowed) Junior Professorship from 2019-2021. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007). Before joining Georgia Tech in 2015, Dr. Krishna spent a year as a researcher at the VSSAD group at Intel, Massachusetts.
Dr. Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems. His research is funded via multiple awards from NSF, DARPA, IARPA, Department of Energy, Intel, Google, Facebook, Qualcomm and TSMC. His papers have been cited over 11,000 times. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and four have won best paper awards. He was inducted into the HPCA Hall of Fame in 2022. He received the “Class of 1940 Course Survey Teaching Effectiveness” Award from Georgia Tech in 2018 and the “Roger P. Webb Outstanding Junior Faculty Award” from the School of ECE in Georgia Tech in 2021.

Keynote 2: Practical Advice for a Successful and Happy Career in Research

Speaker: Martin Maas (Google Research)

Abstract: As scientists, we strive to take an intentional and mindful approach to research, whether we are running an experiment or writing a research paper. However, a similarly intentional and mindful approach is required when it comes to our career choices and selecting the problems we work on. In this talk, I will reflect on common trade-offs associated with these decisions and distill them into practical advice on balancing different objectives of a research career.

Bio: Martin Maas is a Staff Research Scientist at Google Research, where he is part of the Google Brain team. His research interests are in language runtimes, computer architecture, systems, and machine learning, with a focus on applying machine learning to systems problems. He also chairs the J Extension group within the RISC-V project, which investigates hardware extensions for managed runtimes. Martin holds a BA in Computer Science from the University of Cambridge, as well as MS and PhD degrees in Computer Science from the University of California at Berkeley, where he worked on hardware support for managed languages and architectural support for memory-trace obliviousness.

Panel Discussion: Demystifying Grad School

ACCEPTED PAPERS:

• Analyzing Secure Non-Volatile Memory (Lightning, Poster)
  Chia Jen Cheng (Boston University); Samuel Thomas (Brown University); Tali Moreshet (Boston University); Maurice Herlihy (Brown University); Iris Bahar (Colorado School of Mines)
• LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators (Lightning, Poster)
  Michael Gilbert; Nellie Wu (MIT); Angshuman Parashar (NVIDIA); Joel Emer (MIT/NVIDIA); Vivienne Sze (MIT)
• Leveraging Causality for Server Resource Provisioning (Lightning, Poster)
  Varun Gohil (Massachusetts Institute of Technology); Sundar Dev; David Lo; Parthasarathy Ranganathan (Google); Christina Delimitrou (Massachusetts Institute of Technology)
• A Neuromorphic Architecture for Online Learning in Brain-Computer Interfaces (Lightning, Poster)
  Michał Gerasimiuk; Andrew Milas; Karthik Sriram (Yale University); Brieuc Balon (Université catholique de Louvain); Ryan Jin (Yale University); James E. Smith (University of Wisconsin (Emeritus)); Abhishek Bhattacharjee (Yale University)
• SplitSim: Scalable and Parallel Full Data Center System Simulations (Lightning, Poster)
  Hejing Li; Antoine Kaufmann (Max Planck Institute for Software Systems)
• CXLMemSim: A pure software simulated CXL.mem for performance characterization (Lightning, Slides, Poster)
  Yiwei Yang; Pooneh Safayenikoo (University of California, Santa Cruz); Jiacheng Ma; Tanvir Ahmed Khan (University of Michigan); Andrew Quinn (University of California, Santa Cruz)
• SMAD: Efficiently Defending Against Transient Execution Attacks (Lightning, Poster)
  Ange Thierry Ishimwe; Tamara Lehman (University of Colorado Boulder)
• Hardware for Event-driven Architectures (Slides)
  David Schall (University of Edinburgh)
• HammerSim: A Tool to Model Rowhammer (Slides)
  Kaustav Goswami; Ayaz Akram; Hari Venugopalan; Jason Lowe-Power (University of California, Davis)
• Formal Pre-silicon Verification of Processors and Hardware Accelerators (Slides)
  Saranyu Chattopadhyay; Caroline Trippel; Clark Barrett; Subhasish Mitra (Stanford University)
• Probabilistic Memory Consistency Specifications (Slides)
  Reese Levine (UC Santa Cruz)
• Dataflow Blocks: Modular Time-Multiplexing for CGRAs (Slides)
  Xuesi Chen; Nishanth Subramanian; Karthik Ramanathan; Nathan Beckmann; Brandon Lucia (Carnegie Mellon University)
• Optimizing Temporal Motif Mining On A GPU (Slides)
  Yichao Yuan; Haojie Ye (University of Michigan); Sanketh Vedula (Technion); Nishil Talati (University of Michigan/AMD Research)
• Formal Characterization of Hardware Transmitters for Secure Software and Hardware Repair (Slides)
  Yao Hsiao (Stanford University); Christopher Fletcher (University of Illinois at Urbana-Champaign); Caroline Trippel (Stanford University)
• A Case for Aggressive Speculative Execution for VQA Optimization
  Suhas K Vittal (Georgia Tech)
• Hardware Support for Efficient and Secure Resource Harvesting in the Cloud (Slides)
  Jovan Stojkovic (UIUC); Chunao Liu; Muhammad Shahbaz (Purdue University); Josep Torrellas (UIUC)
• Exploiting Data Commonality in Value Prediction (Slides)
  Haiyue Ma; David Wentzlaff (Princeton University)
• Dynamic Speculation Control of Modern Processors (Slides)
  Sankara Prasad Ramesh; Dean Tullsen (University of California San Diego)
• Minimal System-Level Test Synthesis from RTL for Hyperscale SDC Detection
  Brandon D'Agostino; Subhasish Mitra; Caroline Trippel (Stanford University)
• Near-Memory Acceleration of Far Memory (Slides)
  Neel Patel; Mohammad Alian (University of Kansas)
• Accelerating Sparse Tensor Algebra by Overbooking Buffer Occupancy (Slides)
  Fisher Xue; Nellie Wu (MIT); Joel Emer (MIT/NVIDIA); Vivienne Sze (MIT)
• Detecting Microarchitectural Vulnerabilities via Fuzz Testing of White-box CPUs (Slides)
  Bo Fu; Alaa Alameldeen (Simon Fraser University); Gururaj Saileshwar (University of Toronto/NVIDIA Research)
• ConstSpec: Mitigating Cache-based Spectre Attacks via Fine-Gain Constant-Time Accesses (Slides)
  Arash Pashrashid; Trevor E. Carlson (National University of Singapore)

SUBMIT

Eligibility

Applicants must be either (a) research-active undergraduate students aiming for graduate school, or (b) graduate students (Masters and/or PhD) in computer architecture and related fields who have completed less than 3 years of graduate school at the time of the workshop. A note from the student’s research advisor attesting this is required as part of the submission.

Eligible students are invited to submit their early stage or on-going work to this workshop. Submitted work should not have been presented as part of a prior ACM/IEEE conference.

Note: This workshop is not a venue for publication and there will be no formal proceedings.

Topics of Interest

The workshop invites papers from all areas of computer architecture, broadly defined. Topics of interest include, but not limited to:

• Datacenter systems
• Hardware acceleration
• Memory hierarchy
• Virtualization
• Security
• Microarchitecture
• GPUs
• Parallel architectures
• Emerging technologies

Submission Guidelines

The goal of this workshop is to help students think about a problem/idea in an holistic manner and communicate your ideas to the wider community, so that we can provide some valuable early-stage feedback. To this end, we encourage you to cover the following aspects in your submission:

• Scope of problem/idea: Provide clear context for and scope of the problem(s) or idea(s) you intend to work on. This will likely form the basis of the introduction/background sections of your future work(s).
• Solution: Provide an overview of the design and implementation aspects of your solution(s) to the problem(s) described above. Given this is on-going work, focus more on providing breadth than depth. For example, beside describing the design of your idea, enlist the various system aspects which your proposed solutions will affect (e.g. does your proposed solution affect coherence protocols?) and that if you plan to discuss these effects in your future submission(s).
• Evaluation methodology: Discuss the evaluation methodology you plan to adopt to test the efficacy of your ideas. For example, the workloads that you plan to use, the tools you’ll employ (e.g., architectural simulator, real world experiments, FPGA prototypes), etc.
• Related work: This can be the traditional related work section. Please specify if you plan to quantitatively compare against some prior work.

Submission Details

• Submissions must be PDF files, in 2-column, single-spaced, 10pt format, at most 2 pages long, not including references.
• Submissions are double-blind. Please do not have any author identifying information in the paper submitted.
• Please have your research advisor send the workshop organizers an email with the following subject line “<Your name> meets YArch’23 eligibility requirements” to youngarchitectw@gmail.com.
• Submission site: https://yarch2023.hotcrp.com
• Registration deadline: January 20th, 2023, 23:59pm EST
• Submission deadline: January 27th, 2023, 23:59pm EST

Declaring Conflicts

When registering a submission, all its co-authors must provide information about conflicts with the YArch’23 program committee members. You are conflicted with a member if:

1. you are currently employed at the same institution, have been previously employed at the same institution within the past two years (2020 or later), or are going to begin employment at the same institution;
2. you have a past or present association as thesis advisor or advisee (no time limit);
3. you have collaborated on a project, publication, grant proposal, or editorship within the past two years (2020 or later);
4. or, you have spouse or first-degree relative relations.

Sponsors: