Equipment
Lab and Coral NameTRL / EV620
ModelElectronic Visions
SpecialistDennis Ward     (Kristofor Payer)
Physical Location4F Bonding
Classification
Process CategoryPhoto
SubcategoryBond
Material KeywordsSilicon, Pyrex
Sample Size6" Wafers, 4" Wafers, Pieces
Alternativenone
Keywordssingle wafer, manual load, top side of sample, manual operation, alignment
Description
EV620 is a wafer aligner/bonder that is used for aligning wafers for the EV501 bond tool or for bonding wafers with silicon-direct bonding mode. The tool operates similar to the EV1. Dust particles, wafer bow, or bad luck can lead to bubbles in the bond interface.

Best forWafer alignment before bonding (fusion, anodic, thermo-compression) or silicon direct bonding
LimitationsIf you want to align wafers, alignment marks are needed on the back side of one of the two wafers. Rough surfaces won't bond (though CMP can sometimes smooth it enough).
Characteristics/FOM
Caution withCleanliness, quartz plate alignment (lots of breakages lately), teflon chucks are for non-heated fusion bond processing only (heated bonds use metal chucks). Cleanliness is essential, as particles will ruin your bond.
Machine Charges6/wafer
Documents

SOP
Resist RecipesBaseline resist recipes for TRL

Documents
Anoidc BondingOriginal paper on anodic bonding

External Links
GuideMicroChem Application Notes
Process Matrix Details

Permitted
Been in the ALDSamples that have been in any of the ALD systems
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Pyrex SubstratesPyrex substrates can be a concern due to high sodium content, which contaminates CMOS frontend tools
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III-V SubstratesAny III-V substrates, e.g. GaAs, GaN, InP, and so on. Note though that many common III-V substrates will also carry the Au flag, but there are some GREEN III-V substrates.
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Germanium on surfaceSamples with germanium on the surface (typically grown films)
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Germanium buriedSamples with germanium buried below a different film
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PiecesWafer pieces may not be handled by the equipment, and are harder to thoroughly clean - preventing them from running in certain tools.
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Gold or RED color codeRED color code substrates. These are gold-contaminated or have been processed in gold contaminated tools. Gold and other metals can contaminate silicon devices (GREEN color code) and have to be separated.
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Any exposure to CMOS metalIf the sample had ever seen a CMOS metal (or a tool that accepts CMOS metal), then some frontend tools could be contaminated by this.
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CMOS metal on surfaceCMOS compatible metals exposed on the surface. These are Al,Ni,Pt,Ti,TiN. Other metals such as Au are *NOT* part of this.
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CMOS metal buriedCMOS compatible metals covered entirely by a different material. These are Al,Ni,Pt,Ti,TiN. Other metals such as Au are *NOT* part of this.
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Been in the STS DRIEThe DRIE etch leaves behind polymer residues on the sidewall ripples, which can be a contamination concern for some tools.
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Been in the SEMA sample viewed in the SEM must have used the appropriate chuck to avoid cross-contamination
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Been in the Concept1The Concep1 deposits dielectrics on GREEN wafers, however it also accepts metal and there can be cross-contamination for diffusion area
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Coming from KOHAfter a KOH etch, the samples must receive a special clean because the K ions are highly contaminating to CMOS frontend tools
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Coming from CMPAfter a CMP, the samples must receive a special clean, because the slurry residues otherwise introduce contamination and particles.


Not Allowed
Ever been in EMLSamples from EML are never permitted to return to ICL or TRL
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Has PhotoresistSamples with photoresist cannot be exposed to high temperatures, which is typical in deposition tools. Outgassing can be a concern.
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Has PolyimidePolyimide is a very chemically resistant polymer, and can tolerate higher temperatures but cannot be exposed to typical PECVD deposition temperatures or diffusion furnaces. Outgassing can be a concern.
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Has Cured SU8Not fully cured SU8 residues can heavily contaminated plasma chambers or destroy other user's samples, but fully cured SU8 is permitted in certain tools.


For more details or help, please consult PTC matrix, email ptc@mtl.mit.edu, or ask the research specialist (Dennis Ward )