Equipment
Lab and Coral NameICL / RTP
ModelAG Associates 8108
SpecialistBernard Alamariu    (Eric Lim)
Physical Location2F 4-South Diffusion
Classification
Process CategoryDiffusion
SubcategoryBake
Material KeywordsSilicon, CMOS Metals
Sample Size6" Wafers, 4" Wafers, Pieces Require Puck
AlternativeICL / RTP-Si
Keywordsmulti wafer, load lock, top side of sample, vacuum, temperature, requires flat
Description
The RTP allows for short anneals with fast temperature ramps in N2, O2, N2/H2, or NH3 ambients. Only 6" Si wafers with no prior history of metal deposition are accepted. Wafer loading to and from cassettes and the process chamber is automated by the tool. Wafer temperature is measured via a pyrometer calibrated for a Si surface requiring that the backside of the wafer to have its Si wafer surface directly exposed. Annealing time/temperature/gas flows must all be specified in a written process recipe.

Best forDopant activation in Si or Ge thin films. Very short oxidation or nitridation processes.
LimitationsWafers with exposed Ge cannot be annealed above 600C.
Characteristics/FOM
Caution with
Machine Charges4/wafer
Documents
Process Matrix Details

Permitted
Been in the ALDSamples that have been in any of the ALD systems
,
Germanium on surfaceSamples with germanium on the surface (typically grown films)
(A),
Germanium buriedSamples with germanium buried below a different film
,
Been in the SEMA sample viewed in the SEM must have used the appropriate chuck to avoid cross-contamination
(With Appropriate Chuck),
Requires ICL RCA CleanAn RCA clean in ICL was carried out immediately before
(Must do)

Not Allowed
Ever been in EMLSamples from EML are never permitted to return to ICL or TRL
,
Pyrex SubstratesPyrex substrates can be a concern due to high sodium content, which contaminates CMOS frontend tools
,
III-V SubstratesAny III-V substrates, e.g. GaAs, GaN, InP, and so on. Note though that many common III-V substrates will also carry the Au flag, but there are some GREEN III-V substrates.
,
PiecesWafer pieces may not be handled by the equipment, and are harder to thoroughly clean - preventing them from running in certain tools.
,
Gold or RED color codeRED color code substrates. These are gold-contaminated or have been processed in gold contaminated tools. Gold and other metals can contaminate silicon devices (GREEN color code) and have to be separated.
,
Any exposure to CMOS metalIf the sample had ever seen a CMOS metal (or a tool that accepts CMOS metal), then some frontend tools could be contaminated by this.
,
CMOS metal on surfaceCMOS compatible metals exposed on the surface. These are Al,Ni,Pt,Ti,TiN. Other metals such as Au are *NOT* part of this.
,
CMOS metal buriedCMOS compatible metals covered entirely by a different material. These are Al,Ni,Pt,Ti,TiN. Other metals such as Au are *NOT* part of this.
,
Been in the STS DRIEThe DRIE etch leaves behind polymer residues on the sidewall ripples, which can be a contamination concern for some tools.
,
Been in the Concept1The Concep1 deposits dielectrics on GREEN wafers, however it also accepts metal and there can be cross-contamination for diffusion area
,
Has PhotoresistSamples with photoresist cannot be exposed to high temperatures, which is typical in deposition tools. Outgassing can be a concern.
,
Has PolyimidePolyimide is a very chemically resistant polymer, and can tolerate higher temperatures but cannot be exposed to typical PECVD deposition temperatures or diffusion furnaces. Outgassing can be a concern.
,
Has Cured SU8Not fully cured SU8 residues can heavily contaminated plasma chambers or destroy other user's samples, but fully cured SU8 is permitted in certain tools.
,
Coming from KOHAfter a KOH etch, the samples must receive a special clean because the K ions are highly contaminating to CMOS frontend tools
,
Coming from CMPAfter a CMP, the samples must receive a special clean, because the slurry residues otherwise introduce contamination and particles.
,
Has been past RCA clean for over 4 hoursFor some diffusion furnaces, the samples must immideatly enter the furnace and cannot be stored in a box for a long time.


For more details or help, please consult PTC matrix, email ptc@mtl.mit.edu, or ask the research specialist (Bernard Alamariu)