Equipment
| Lab and Coral Name | TRL / RTA-HiT |
| Model | TBD |
| Specialist | Bernard Alamariu (Eric Lim) |
| Physical Location | 4F Main-South |
Classification
| Process Category | Diffusion |
| Subcategory | Bake |
| Material Keywords | Silicon, III-V, GaN, CMOS Metals, Non-CMOS Metals |
| Sample Size | 6" Wafers, 4" Wafers, Pieces |
| Alternative | rta-pieces |
| Keywords | single wafer, manual load, multiple pieces, top side of sample, vacuum, temperature |
Description
The rta35 is a rapid thermal annealer for III-V materials. Temperature in the chamber is measured using thermocouple. Single or multiple small pieces can be annealed at a time. The annealing is done under N2 ambient.
| Best for | Alloying Ohmics, Annealing dieletrics (Si3N4, SiO2…) |
| Limitations | Small pieces |
| Characteristics/FOM | Flash based annealing oven with controlled and stable chamber temperature |
| Caution with | PR and any polymer is not strictly prohibited |
| Machine Charges | 4/wafer |
Documents
Process Matrix Details
Permitted
Been in the ALDSamples that have been in any of the ALD systems
, III-V SubstratesAny III-V substrates, e.g. GaAs, GaN, InP, and so on. Note though that many common III-V substrates will also carry the Au flag, but there are some GREEN III-V substrates.
, Germanium on surfaceSamples with germanium on the surface (typically grown films)
(A), Germanium buriedSamples with germanium buried below a different film
, PiecesWafer pieces may not be handled by the equipment, and are harder to thoroughly clean - preventing them from running in certain tools.
, Gold or RED color codeRED color code substrates. These are gold-contaminated or have been processed in gold contaminated tools. Gold and other metals can contaminate silicon devices (GREEN color code) and have to be separated.
(Adds), Any exposure to CMOS metalIf the sample had ever seen a CMOS metal (or a tool that accepts CMOS metal), then some frontend tools could be contaminated by this.
(Adds), CMOS metal on surfaceCMOS compatible metals exposed on the surface. These are Al,Ni,Pt,Ti,TiN. Other metals such as Au are *NOT* part of this.
, CMOS metal buriedCMOS compatible metals covered entirely by a different material. These are Al,Ni,Pt,Ti,TiN. Other metals such as Au are *NOT* part of this.
, Been in the STS DRIEThe DRIE etch leaves behind polymer residues on the sidewall ripples, which can be a contamination concern for some tools.
, Been in the SEMA sample viewed in the SEM must have used the appropriate chuck to avoid cross-contamination
(With Appropriate Chuck), Been in the Concept1The Concep1 deposits dielectrics on GREEN wafers, however it also accepts metal and there can be cross-contamination for diffusion area
, Coming from KOHAfter a KOH etch, the samples must receive a special clean because the K ions are highly contaminating to CMOS frontend tools
, Coming from CMPAfter a CMP, the samples must receive a special clean, because the slurry residues otherwise introduce contamination and particles.
Not Allowed
Ever been in EMLSamples from EML are never permitted to return to ICL or TRL
, Pyrex SubstratesPyrex substrates can be a concern due to high sodium content, which contaminates CMOS frontend tools
, Has PhotoresistSamples with photoresist cannot be exposed to high temperatures, which is typical in deposition tools. Outgassing can be a concern.
, Has PolyimidePolyimide is a very chemically resistant polymer, and can tolerate higher temperatures but cannot be exposed to typical PECVD deposition temperatures or diffusion furnaces. Outgassing can be a concern.
, Has Cured SU8Not fully cured SU8 residues can heavily contaminated plasma chambers or destroy other user's samples, but fully cured SU8 is permitted in certain tools.
For more details or help, please consult PTC matrix, email ptc@mtl.mit.edu, or ask the research specialist (Bernard Alamariu)